Datasheet

AD7304/AD7305
Rev. C | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
OUT
B
1
V
OUT
A 2
V
SS
3
V
REF
A 4
V
OUT
C
16
V
OUT
D 15
V
DD
14
V
REF
C 13
V
REF
B 5 V
REF
D 12
GND
6
SDI/SHDN
11
LDAC
7
CLK
10
CLR
8
CS
9
AD7304
TOP VIEW
(Not to Scale)
01114-008
Figure 8. AD7304 Pin Configuration
Table 7. AD7304 Pin Function Descriptions
Pin No. Mnemonic Description
1 V
OUT
B
Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V
REF
B pin.
Output is open circuit when SHDN is enabled.
2 V
OUT
A
Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V
REF
A pin.
Output is open circuit when SHDN is enabled.
3 V
SS
Negative Power Supply Input. Specified range of operation is 0 V to −5.5 V.
4 V
REF
A Channel A Reference Input. Establishes V
OUT
A full-scale voltage. Specified range of operation is V
SS
< V
REF
A < V
DD
.
5 V
REF
B Channel B Reference Input. Establishes V
OUT
B full-scale voltage. Specified range of operation is V
SS
< V
REF
B < V
DD
.
6 GND Common Analog and Digital Ground.
7
LDAC Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the
corresponding DAC registers. Asynchronous active low input. DAC register is transparent when
LDAC = 0. See
Table 4 for operation.
8
CLR Clears All Input and DAC Registers to the Zero Condition. Asynchronous active low input. The serial register is
not effected.
9
CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial input register data to
the decoded input register when
CS returns high. Does not effect LDAC operation.
10 CLK
Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select
CS.
11 SDI/SHDN
Serial Data Input Loads Directly into the Shift Register, MSB First. Hardware shutdown (SHDN) control input,
active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as
power is present on V
DD
.
12 V
REF
D Channel D Reference Input. Establishes V
OUT
D full-scale voltage. Specified range of operation is V
SS
< V
REF
D < V
DD
.
13 V
REF
C Channel C Reference Input. Establishes V
OUT
C full-scale voltage. Specified range of operation is V
SS
V
REF
C < V
DD
.
14 V
DD
Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
15 V
OUT
D
Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V
REF
D pin.
Output is open circuit when SHDN is enabled.
16 V
OUT
C
Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V
REF
C pin.
Output is open circuit when SHDN is enabled.