Datasheet

AD7304/AD7305
Rev. C | Page 16 of 20
AD7305 PARALLEL DATA INTERFACE
The AD7305 has an 8-bit parallel interface DB7 = MSB, DB0 =
LSB. Two address bits, A1 and A0, are decoded when an active
low write strobe is placed on the
WR
pin, see Table 6. The
WR
is a level-sensitive input pin, therefore, the data setup and data
hold times defined in the Timing Specifications section need to
be adhered to.
AD7305
8
320k Ω
280k Ω
80kΩ
640k Ω
680k Ω
V
DD
LDAC
V
SS
WR
V
DD
V
REF
GND
DATA
DB0–DB7
A1
A0/SHDN
R
R
R
R
POWER-
ON
RESET
DAC A
OE
DAC A
REGISTER
DAC B
OE
DAC B
REGISTER
DAC C
OE
DAC C
REGISTER
DAC D
OE
DAC D
REGISTER
DAC A
B
C
D
2:4
DECODE
V
OUT
C
V
OUT
B
V
OUT
A
V
OUT
D
01114-036
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
R
R
R
R
Figure 36. AD7305 Equivalent Logic Interface
The
LDAC
pin provides the capability of simultaneously
updating all DAC registers with new data from the input
registers at the same time. This results in the analog outputs all
changing to their new values at the same time. The
LDAC
pin is
a level-sensitive input. If the simultaneous update feature is not
required, the
LDAC
pin can be tied to logic low. When the
LDAC
is tied to Logic Low, the DAC registers become
transparent and the input register data determines the DAC
output voltage (see Figure 36 for an equivalent interface logic
diagram).
AD7226 PIN COMPATIBILITY
By tying the
LDAC
pin to ground, the AD7305 has the same pin
configuration and functionality as the AD7226, with the
exception of a lower power supply operating voltage.
AD7305 HARDWARE SHUTDOWN SHDN
If a three-state driver is used on the A0/SHDN pin, the AD7305
can be placed into a power shutdown mode when the A0/SHDN
pin is placed in a high impedance state. For proper operation,
no other termination voltages should be present on this pin. An
internal window comparator detects when the logic voltage on
the SHDN pin is between 28% and 36% of V
DD
. A high imped-
ance, internal-bias generator provides this voltage on the SHDN
pin. The four DAC output voltages become high impedance
with a nominal resistance of 120 kΩ to ground.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND). The V
REF
pins also contain a back-
biased ESD protection Zener connected to V
DD
(see Figure 37).
GND
DIGITA
L
INPUTS
V
DD
V
REF
X
01114-037
Figure 37. Equivalent ESD Protection Circuits