Datasheet

AD7303
–3–
REV. 0
TIMING CHARACTERISTICS
1, 2
Parameter Limit at T
MIN
, T
MAX
(B Version) Units Conditions/Comments
t
1
33 ns min SCLK Cycle Time
t
2
13 ns min SCLK High Time
t
3
13 ns min SCLK Low Time
t
4
5 ns min SYNC Setup Time
t
5
5 ns min Data Setup Time
t
6
4.5 ns min Data Hold Time
t
7
4.5 ns min SYNC Hold Time
t
8
33 ns min Minimum SYNC High Time
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2,
tr and tf should not exceed 1 µs on any input.
2
See Figures 1 and 2.
SCLK (I)
SYNC (I)
DIN (I)
DB15
DB0
t
5
t
6
t
2
t
3
t
4
t
7
t
4
t
8
t
1
Figure 1. Timing Diagram for Continuous 16-Bit Write
SCLK (I)
SYNC (I)
DIN (I)
DB15 DB8
t
5
t
6
t
2
t
3
t
4
t
7
DB7 DB0
t
5
t
6
t
8
t
1
Figure 2. Timing Diagram for 2 × 8-Bit Writes
(V
DD
= +2.7 V to +5.5 V; GND = 0 V; Reference = Internal V
DD
/2 Reference; all specifications
T
MIN
to T
MAX
unless otherwise noted)