Datasheet

AD7302
–9–
REV. 0
GENERAL DESCRIPTION
D/A Section
The AD7302 is a dual 8-bit voltage output digital-to-analog
converter. The architecture consists of a reference amplifier, a
current source DAC followed by a current-to-voltage converter
capable of generating rail-to-rail voltages on the output of the
DAC. Figure 19 shows a block diagram of the basic DAC
architecture.
REFERENCE
AMPLIFIER
+
-
V
O
A/B
V
DD
REFIN
AD7302
CURRENT
DAC
I/V
30kΩ
30kΩ
11.7kΩ
11.7kΩ
Figure 19. DAC Architecture
Both DAC A and DAC B outputs are internally buffered and
these output buffer amplifiers have rail-to-rail output character-
istics. The output amplifier is capable driving a load of 10 kΩ to
both V
DD
and ground in parallel with a 100 pF to ground. The
reference selection for the DAC can either be internally generated
from V
DD
or externally applied through the REFIN pin. A
comparator on the REFIN pin detects whether the required
reference is the internally generated reference or the externally
applied voltage to the REFIN pin. If REFIN is connected to
V
DD
, the reference selected is the internally generated V
DD
/2
reference. When an externally applied voltage is more than one
volt below V
DD
, the comparator selection switches to the
externally applied voltage to the REFIN pin. The range on the
external reference input is from 1.0 V to V
DD
/2. The output
voltage from either DAC is given by:
V
O
A/B = 2 × V
REF
× (N/256)
where:
V
REF
is the voltage applied to the external REFIN pin or
V
DD
/2 when the internal reference is selected.
␣␣ N is the decimal equivalent of the code loaded to the DAC
register and ranges from 0 to 255.
Reference
The AD7302 has the facility to use either an external reference
applied through the REFIN pin or an internal reference
generated from V
DD
. Figure 20 shows the reference input
arrangement where either the internal V
DD
/2 reference or the
externally applied reference can be selected.
COMPARATOR
VTH
PMOS
MUX
INT
REF
SELECTED
REFERENCE OUTPUT
V
DD
REF
IN
INT REF
EXT REF
Figure 20. Reference Selection Circuitry
The internal reference is selected by tying the REFIN pin to
V
DD
. If an external reference is to be used, this can be directly
applied to the REFIN pin; if this is 1 V below V
DD
, the internal
circuitry will select this externally applied reference as the
reference source for the DAC.
Digital Interface
The AD7302 contains a fast parallel interface allowing this dual
DAC to interface to industry standard microprocessors, micro-
controllers and DSP machines. There are two modes in which
this parallel interface can be configured to update the DAC
outputs. The simultaneous update mode allows simultaneous
updating of both DAC outputs. The automatic update mode
allows each DAC to be individually updated following a write
cycle. Figure 21 shows the internal logic associated with the
digital interface. The PON STRB signal is internally generated
from the power on reset circuitry and is low during the power-
on reset phase of the power-up procedure.
CLR
PON STRB
LDAC
A/B
CS
WR
CLEAR
LDAC
DAC A SEL
DAC A
CONTROL
LOGIC
ENABLE
SET SLE
MLE A
SLE A
CLR
CLEAR
LDAC
DAC B SEL
DAC B
CONTROL
LOGIC
ENABLE
SET SLE
MLE B
SLE B
Figure 21. Logic Interface
The AD7302 has a double buffered interface, which allows
for simultaneous updating of the DAC outputs. Figure 22 shows
a block diagram of the register arrangement within the AD7302.
DB7–DB0
INPUT
REGISTER
LOWER
NIBBLE
4 TO 15
DECODER
DAC
REGISTER
DRIVERS
4
15
15
30
8
UPPER
NIBBLE
4 TO 15
DECODER
DAC
REGISTER
DRIVERS
4
15
15
30
CONTROL
LOGIC
SLEMLE
A/B
CS
WR
LDAC
CLR
Figure 22. Register Arrangement