Datasheet

AD7298-1
Rev. A | Page 5 of 24
TIMING SPECIFICATIONS
V
DD
= 2.8 V to 3.6 V, V
DRIVE
= 1.65 V to 3.6 V, V
REF
= 2.5 V internal, T
A
= −40°C to +125°C, unless otherwise noted. Sample tested during
initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DRIVE
) and timed from a voltage level
of 1.6 V.
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Test Conditions/Comments
t
CONVERT
t
2
+ (16 × t
SCLK
) µs max Conversion time
820 ns typ Each ADC channel V
IN0
to V
IN7
, f
SCLK
= 20 MHz
f
SCLK
1
50 kHz min Frequency of external serial clock
20 MHz max Frequency of external serial clock
t
QUIET
6 ns min Minimum quiet time required between the end of the serial read and the start of
the next voltage conversion in repeat and nonrepeat mode.
t
2
10 ns min
CS
to SCLK setup time
t
3
1
15 ns max Delay from
CS
(falling edge) until DOUT three-state disabled
t
4
1
Data access time after SCLK falling edge
35 ns max V
DRIVE
= 1.65 V to 3 V
28 ns max V
DRIVE
= 3 V to 3.6 V
t
5
0.4 × t
SCLK
ns min SCLK low pulse width
t
6
0.4 × t
SCLK
ns min SCLK high pulse width
t
7
1
14 ns min SCLK to DOUT valid hold time
t
8
1
16/34 ns min/ns max SCLK falling edge to DOUT high impedance
t
9
5 ns min DIN setup time prior to SCLK falling edge
t
10
4 ns min DIN hold time after SCLK falling edge
t
11
1
30 ns max Delay from
CS
rising edge to DOUT high impedance
t
POWER-UP
6 ms max Internal reference power-up time from full power-down
1
Measured with a load capacitance on DOUT of 15 pF.