Datasheet

AD7294 Data Sheet
Rev. H | Page 30 of 48
DAC
A
, DAC
B
, DAC
C
, DAC
D
, REGISTERS (0x01 TO 0x04)
Writing to these register addresses sets the DAC
A
, DAC
B
, DAC
C
,
and DAC
D
output voltage codes, respectively. Bits[D11:D0] in
the write result register are the data bits sent to DAC
A
. Bit D15
to Bit D12 are ignored.
Table 17. DAC Register (First Write)
1
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8
X X X X B11 B10 B9 B8
1
X is don’t care.
Table 18. DAC Register (Second Write)
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0
ALERT STATUS REGISTER A (0x05), REGISTER B
(0x06), AND REGISTER C (0x07)
The alert status registers (A, B, and C) are 8-bit read/write
registers that provide information on an alert event. If a
conversion results in activating the ALERT/BUSY pin or the
alert_flag bit in the result register or T
SENSE
registers, the alert
status register can be read to gain further information. To clear
the full content of any one of the alert registers, write a code of
FF (all ones) to the relevant registers. Alternatively, the user can
write to the respective alert bit in the selected alert register to
clear the alert associated with that bit. The entire contents of all
the alert status registers can be cleared by writing a 1 to Bit D1
and Bit D2 in the configuration register, as shown in Table 24.
However, this operation then enables the ALERT/BUSY pin for
subsequent conversions. See the Alerts and Limits Theory
section for more details.
CHANNEL SEQUENCE REGISTER (0x08)
The channel sequence register is an 8-bit read/write register that
allows the user to sequence the ADC conversions to be per-
formed in autocycle mode. Table 22 shows the content of the
channel sequence register. See the Modes of Operation section
for more information.
Table 19. Alert Status Register A
Alert Bit D7 D6 D5 D4 D3 D2 D1 D0
Function
V
IN
3
high alert
V
IN
3
low alert
V
IN
2
high alert
V
IN
2
low alert
V
IN
1
high alert
V
IN
1
low alert
V
IN
0
high alert
V
IN
0
low alert
Table 20. Alert Status Register B
Alert Bit D7 D6 D5 D4 D3 D2 D1 D0
Function
Reserved Reserved I
SENSE
2
overrange
I
SENSE
1
overrange
I
SENSE
2
high alert
I
SENSE
2
low alert
I
SENSE
1
high alert
I
SENSE
1
low alert
Table 21. Alert Status Register C
Alert Bit D7 D6 D5 D4 D3 D2 D1 D0
Function
Open-diode
flag
Overtemp
alert
T
SENSE
INT
high alert
T
SENSE
INT
low alert
T
SENSE
2
high alert
T
SENSE
2
low alert
T
SENSE
1
high alert
T
SENSE
1
low alert
Table 22. Channel Sequence Register
Channel Bit D7 D6 D5 D4 D3 D2 D1 D0
Function
Reserved Reserved
I
SENSE
2 I
SENSE
1 V
IN
3 V
IN
2 V
IN
1 V
IN
0