Datasheet

Data Sheet AD7294
Rev. H | Page 9 of 48
TIMING CHARACTERISTICS
I
2
C Serial Interface
AV
DD
= DV
DD
= 4.5 V to 5.5 V, AGND = DGND = 0 V, V
REF
= 2.5 V internal or external; V
DRIVE
= 2.7 V to 5.5 V; V
PP
= AV
DD
to 59.4 V;
DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; T
A
=
−40°C to +105°C, unless otherwise noted.
Table 4.
Parameter
1
Limit at T
MIN
, T
MAX
Unit Description
f
SCL
400 kHz max SCL clock frequency
t
1
2.5 µs min SCL cycle time
t
2
0.6 µs min t
HIGH
, SCL high time
t
3
1.3 µs min t
LOW
, SCL low time
t
4
0.6 µs min t
HD,STA
, start/repeated start condition hold time
t
5
100 ns min t
SU, DAT
, data setup time
t
6
0.9 µs max t
HD, DAT
, data hold time
0 µs min t
HD, DAT
, data hold time
t
7
0.6 µs min t
SU,STA
, setup time for repeated start
t
8
0.6 µs min t
SU,STO
, stop condition setup time
t
9
1.3 µs min t
BUF
, bus free time between a stop and a start condition
t
10
300 ns max t
R
, rise time of SCL and SDA when receiving
0 ns min t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
11
300 ns max t
F
, fall time of SDA when transmitting
0 ns min t
F
, fall time of SDA when receiving (CMOS compatible)
300 ns max t
F
, fall time of SCL and SDA when receiving
20 + 0.1C
b
2
ns min t
F
, fall time of SCL and SDA when transmitting
C
b
400 pF max Capacitive load for each bus line
1
See Figure 2.
2
C
b
is the total capacitance in pF of one bus line. t
R
and t
F
are measured between 0.3 DV
DD
and 0.7 DV
DD
.
Timing and Circuit Diagrams
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
9
t
3
t
1
t
11
t
4
t
10
t
4
t
5
t
7
t
6
t
8
t
2
SDA
SCL
05747-002
Figure 2. I
2
C-Compatible Serial Interface Timing Diagram
C
L
50pF
TO OUTPUT PIN
V
OH
(MIN) OR
V
OL
(MAX)
200µA
200µA
I
OL
I
OH
05747-003
Figure 3. Load Circuit for Digital Output