2-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense AD7294 Data Sheet FEATURES APPLICATIONS 12-bit SAR ADC with 3 μs conversion time 4 uncommitted analog inputs Differential/single-ended VREF, 2 × VREF input ranges 2 high-side current sense inputs 5 V to 59.4 V operating range 0.
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AD7294 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 TSENSE1, TSENSE2 Result Registers (0x02 and 0x03) ....................... 29 Applications ....................................................................................... 1 TSENSEINT Result Register (0x04).............................................. 29 General Description .........................................................................
Data Sheet AD7294 REVISION HISTORY 1/12—Rev. G to Rev. H Changes to Table 2 ............................................................................ 6 11/11—Rev. F to Rev. G Change to DAC Output Characteristics Parameter of Table 1 ................................................................................................. 5 Deleted DAC HIGH-Z Pin Leakage from Table 3 ........................ 8 Change to Figure 4 ..........................................................................
AD7294 Data Sheet FUNCTIONAL BLOCK DIAGRAM RSENSE VPP(1 TO 2) RS1(+) RS1(–) RS2(+) HIGH SIDE CURRENT SENSE ISENSE 2 OVERRANGE AVDD AGND DAC OUT (1 TO 6) (1 TO 7) V+ AB/CD 2.5V REF HIGH SIDE CURRENT SENSE 12-BIT DAC 100kΩ 200kΩ VOUTA VREF 10.
Data Sheet AD7294 SPECIFICATIONS DAC SPECIFICATIONS AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, internal 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; TA =−40°C to +105°C, unless otherwise noted. DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V, OFFSET IN x is floating, therefore, the DAC output span = 0 V to 5 V. Table 1.
AD7294 Data Sheet ADC SPECIFICATIONS AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, VREF = 2.5 V internal or external; VDRIVE = 2.7 V to 5.5 V; VPP = AVDD to 59.4 V; TA = −40°C to +105°C, unless otherwise noted. Table 2.
Data Sheet Parameter TEMPERATURE SENSOR—INTERNAL Operating Range Accuracy Resolution Update Rate TEMPERATURE SENSOR—EXTERNAL Operating Range Accuracy Resolution Low Level Output Current Source2 Medium Level Output Current Source2 High Level Output Current Source2 Maximum Series Resistance (RS) for External Diode2 Maximum Parallel Capacitance (CP) for External Diode2 CURRENT SENSE VPP Supply Range Gain RS(+)/RS(−) Input Bias Current CMRR/PSRR2 Offset Error Offset Drift Amplifier Peak-To-Peak Noise2 VPP Suppl
AD7294 Data Sheet GENERAL SPECIFICATIONS AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, VREF = 2.5 V internal or external; VDRIVE = 2.7 V to 5.5 V; VPP = AVDD to 59.4 V; DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; TA = −40°C to +105°C, unless otherwise noted. Table 3.
Data Sheet AD7294 TIMING CHARACTERISTICS I2C Serial Interface AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, VREF = 2.5 V internal or external; VDRIVE = 2.7 V to 5.5 V; VPP = AVDD to 59.4 V; DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; TA = −40°C to +105°C, unless otherwise noted. Table 4. Parameter1 fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Cb 1 2 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.
AD7294 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.1 Table 5.
Data Sheet AD7294 VIN3 VIN2 VIN1 REF OUT/REFIN ADC VIN0 DCAP AVDD5 AGND6 AVDD6 NC AGND7 RS1(+) VPP1 RS1(–) VPP2 NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC 1 PIN 1 INDICATOR RS2(–) 2 48 DGND 47 RS2(+) 3 46 DGND ISENSE 1 OVERRANGE NC 4 AVDD1 5 45 ISENSE 2 OVERRANGE 44 DVDD AGND1 6 43 DGND AGND2 7 AD7294 42 VDRIVE AVDD2 8 TQFP TOP VIEW (Not to Scale) 41 OPGND 40 SCL 39 SDA D1+ 11 38 AS0 D1– 12 37 AS1 A
AD7294 Data Sheet Table 7. Pin Function Descriptions TQFP Pin No. 2, 61 3, 60 1, 4, 16, 17, 32, 33, 59, 64 5, 8, 14, 25, 56, 57 LFCSP Pin No. 1, 54 2, 53 3, 52 Mnemonic RS2(−), RS1(−) RS2(+), RS1(+) NC Description Connection for External Shunt Resistor. Connection for External Shunt Resistor. No Connection. Do not connect these pins.
Data Sheet AD7294 TQFP Pin No. 40 LFCSP Pin No. 35 Mnemonic SCL 41 42 36 37 OPGND VDRIVE 43, 47, 48 44 38, 42 39 DGND DVDD 46, 45 41, 40 49, 50, 51, 52 43, 44, 45, 46 ISENSE1 OVERRANGE, ISENSE2 OVERRANGE VIN3 to VIN0 53 47 REFOUT/REFIN ADC 54 48 DCAP 62, 63 55, 56 VPP1, VPP2 EP Exposed Pad Description Serial I2C Bus Clock. The data transfer rate in I2C mode is compatible with both 100 kHz and 400 kHz operating modes. Open-drain input; external pull-up resistor required.
AD7294 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 20 8192 POINT FFT AVDD = DVDD = 5V VDRIVE = 5V, VREF RANGE FSAMPLE = 22.22kSPS FIN = 10kHz, FSCLK = 400kHz SINGLE ENDED SNR = 71dB, THD = –82dB –20 –40 –60 –60 –80 –100 –100 –120 0 2000 4000 6000 8000 10000 FREQUENCY (kHz) –120 0 2000 4000 6000 8000 10000 FREQUENCY (kHz) Figure 6. Signal-to-Noise Ratio Single-Ended, VREF Range Figure 9. Signal-to-Noise Ratio Differential, 2 × VREF Range 20 1.
Data Sheet AD7294 1.0 TA = 25°C VDRIVE = 5V, 2VREF RANGE VREF = 2.5V VDD = 5V SINGLE-ENDED 0.6 0.4 0.2 0.2 INL (LSB) 0.4 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 256 0 512 768 1280 1792 2304 2816 3328 3840 1024 1536 2048 2560 3072 3584 4096 CODE –1.0 05747-078 256 0 512 CODE Figure 12. ADC INL Single-Ended, 2 × VREF Range 1.0 0.6 1.0 0.6 0.4 0.2 0.2 DNL (LSB) 0.4 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.
AD7294 Data Sheet 1.5 0.6 AVDD = DVDD = 5V VDRIVE = 5V, INTERNAL REF, OFFSET IN A/B/C/D = FLOATING 1.0 0.4 MAX INL 0.5 0.2 DNL (LSB) INL (LSB) 0 TA = 25°C VDRIVE = 5V, VREF RANGE VDD = 5V SINGLE-ENDED I2C MODE 400kHz –0.5 –1.0 0 –0.2 –1.5 MIN INL –0.4 0 1 2 3 4 5 6 REFERENCE VOLTAGE (V) –0.6 05747-093 –2.5 256 0 512 768 1280 1792 2304 2816 3328 3840 1024 1536 2048 2560 3072 3584 4096 CODE Figure 18. ADC INL vs. Reference Voltage 05747-080 –2.0 Figure 21. DAC DNL 0.
Data Sheet AD7294 100 64pF 1nF 10nF 0.4 0 –0.2 –0.4 –0.6 40 20 0 –20 –40 AVDD = DVDD = 5V OFFSET IN = FLOATING DAC OUT V = 15V VDRIVE = 5V, INTERNAL REF –60 –80 0 2 4 6 8 10 12 14 16 18 20 TIME (µs) –100 –50 05747-085 –0.8 –40 –30 –20 –10 0 10 20 30 40 50 LOAD CURRENT (mA) Figure 27. DAC Output Voltage vs. Load Current, Input Code = x800 Figure 24. Zoomed in Settling for a ¼ to ¾ Output Voltage Step 1.0 55 DAC A DAC B DAC C DAC D 50 0.7 0.6 0.5 0.4 0.
AD7294 Data Sheet 0 –50 –0.2 –55 –0.4 –60 –65 –0.8 PSRR (dB) –1.0 –1.2 –75 –80 –1.4 –85 –1.6 –90 –1.8 0 0.5 1.0 1.5 2.0 2.5 CAPACITANCE FROM D+ TO D– (nF) –95 1k 05747-065 –2.0 –70 10k 100k 1M 10M FREQUENCY (Hz) 05747-102 ERROR (°C) –0.6 Figure 33. ISENSE Power Supply Rejection Ratio vs. Supply Ripple Frequency Without VPP Supply Decoupling Capacitors for a 500 mV Ripple Figure 30. Temperature Error vs.
Data Sheet AD7294 TERMINOLOGY DAC TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity.
AD7294 Data Sheet THEORY OF OPERATION ADC OVERVIEW 1LSB = 2 × VREF /4096 011...110 ADC CODE 000...001 000...000 111...111 100...010 100...001 100...000 –VREF + 1LSB VREF – 1LSB 05747-017 The AD7294 provides the user with a 9-channel multiplexer, an on-chip track-and-hold, and a successive approximation ADC based around a capacitive DAC. The analog input range for the part can be selected as a 0 V to VREF input or a 2 × VREF input, configured with either single-ended or differential analog inputs.
Data Sheet AD7294 signal so that it is correctly formatted for the ADC. Figure 37 shows a typical connection diagram when operating the ADC in single-ended mode. +2.5V R +1.25V 0V 0V R VIN VIN0 3R –1.25V AD72941 VIN3 REFOUT ADC Driving Differential Inputs 05747-018 0.47µF PINS OMITTED FOR CLARITY. Figure 37. Single-Ended Mode Connection Diagram Differential Mode The AD7294 can have two differential analog input pairs.
AD7294 Data Sheet 440Ω GND 3.75V 2.5V 1.25V 220Ω 2 × VREF p-p V+ 27Ω VREF p-p VIN+ AD72941 VIN+ AD72941 V– V+ A V– 3.75V 2.5V 1.25V 27Ω VIN– DC INPUT VOLTAGE VIN– REFOUT/REFIN ADC REFOUT ADC 0.47µF 10kΩ 0.47µF 20kΩ 05747-023 1ADDITIONAL 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 39.
Data Sheet AD7294 gain. Therefore, for an input voltage of ±200 mV at the pins, an output span of ±2.5 V is generated. The current sensors on the AD7294 are designed to remove any flicker noise and offset present in the sensed signal. This is achieved by implementing a chopping technique that is transparent to the user. The VSENSE signal is first converted by the AD7294, the analog inputs to the amplifiers are then swapped, and the differential voltage is once again converted by the AD7294.
AD7294 Data Sheet Remote Sensing Diode increased about the preset (VREF × 1.2)/12.5. If this occurs, the ISENSE OVERRANGE pin is set to a high logic level enabling appropriate action to be taken to prevent any damage to the external circuitry. The setpoint threshold level is fixed internally in the AD7294, and the current sense amplifier saturates above this level. The comparator also triggers if a voltage of less than AVDD is applied to the RSENSE or VPP pin.
Data Sheet AD7294 Series Resistance Cancellation The DAC word is digitally inverted on-chip such that The AD7294 has been designed to automatically cancel out the effect of parasitic, base, and collector resistance on the temperature reading. This gives a more accurate result, without the need for any user characterization of the parasitic resistance. The AD7294 can compensate for up to 100 Ω in a process that is transparent to the user.
AD7294 Data Sheet The AD7294 can also operate with an external reference. Suitable reference sources for the AD7294 include AD780, AD1582, ADR431, REF193, and ADR391. In addition, choosing a reference with an output trim adjustment, such as the ADR441, allows a system designer to trim system errors by setting a reference voltage to a voltage other than the nominal. Long-term drift is a measure of how much the reference drifts over time.
Data Sheet AD7294 REGISTER SETTING The AD7294 contains internal registers (see Figure 49) that store conversion results, high and low conversion limits, and information to configure and control the device.
AD7294 Data Sheet COMMAND REGISTER (0x00) RESULT REGISTER (0x01) Writing in the command register puts the part into command mode. When in command mode, the part cycles through the selected channels from LSB (D0) to MSB (D7) on each subsequent read (see Table 10). A channel is selected for conversion if a one is written to the desired bit in the command register. On power-up, all bits in the command register are set to zero.
Data Sheet AD7294 ADC Channel Allocation Table 14. TSENSE Register (First Read) The three channel address bits indicate which channel the result in the result register represents. Table 13 details the channel ID bits (S.E. indicates single-ended and DIFF indicates differential). MSB D15 Alert_Flag Table 13. ADC Channel Allocation Table 15. Register (Second Read) Function VIN0 (S.E.) or VIN0 − VIN1 (DIFF) VIN1 (S.E.) or VIN1 − VIN0 (DIFF) VIN2 (S.E.) or VIN2 − VIN3 (DIFF) VIN3 (S.E.
AD7294 Data Sheet DACA, DACB, DACC, DACD, REGISTERS (0x01 TO 0x04) Writing to these register addresses sets the DACA, DACB, DACC, and DACD output voltage codes, respectively. Bits[D11:D0] in the write result register are the data bits sent to DACA. Bit D15 to Bit D12 are ignored. Table 17. DAC Register (First Write)1 MSB D15 X 1 D14 X D13 X D12 X D11 B11 D10 B10 D9 B9 LSB D8 B8 X is don’t care. Table 18.
Data Sheet AD7294 CONFIGURATION REGISTER (0x09) The configuration register is a 16-bit read/write register that sets the operating modes of the AD7294. The bit functions of the configuration register are outlined in Table 23 and Table 24. On power-up, the configuration register is reset to 0x0000. Sample Delay and Bit Trial Delay It is recommended that no I2C bus activity occur when a conversion is taking place; however, this may not be possible, for example, when operating in autocycle mode.
AD7294 Data Sheet POWER-DOWN REGISTER (0x0A) The power-down register is an 8-bit read/write register that powers down various sections on the AD7294 device. On power-up, the default value for the power-down register is 0x30. The content of the power-down register is provided in Table 27. Table 27.
Data Sheet AD7294 TSENSE OFFSET REGISTERS (0x26 AND 0x27) The AD7294 has temperature offset, 8-bit twos complement registers for both Remote Channel TSENSE1 and Remote Channel TSENSE2. It allows the user to add or subtract an offset to the temperature. The offset registers for TSENSE1 and TSENSE2 are 8-bit read/write registers that store data in a twos complement format. This data is subtracted from the temperature readings taken by TSENSE1 and TSENSE2 temperature sensors.
AD7294 Data Sheet I2C INTERFACE GENERAL I2C TIMING communication with a single slave device for the duration of the transaction. Figure 50 shows the timing diagram for general read and write operations using an I2C-compliant interface. The transaction can be used either to write to a slave device (data direction bit = 0) or to read data from it (data direction bit = 1).
Data Sheet AD7294 SERIAL BUS ADDRESS BYTE INTERFACE PROTOCOL The first byte the user writes to the device is the slave address byte. Similar to all I2C-compatible devices, the AD7294 has a 7-bit serial address. The 5 LSBs are user-programmable by the 3 three-state input pins, as shown in Table 34. The AD7294 uses the following I2C protocols. In Table 34, H means tie the pin to VDRIVE, L means tie the pin to DGND, and NC refers to a pin left floating.
AD7294 Data Sheet 1 9 1 9 SCL A6 A5 A4 A3 A2 A1 A0 P7 R/W START BY MASTER P6 P5 P4 P3 P2 P1 P0 ACK. BY AD7294 FRAME 1 SLAVE ADDRESS BYTE ACK. BY AD7294 FRAME 2 ADDRESS POINTER REGISTER BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK.
Data Sheet AD7294 Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers The limit and hysteresis registers (0x0B to 0x25), the result registers (0x01 to 0x04), and the configuration register (0x09) are 16-bit registers; therefore, two bytes of data are required to write a value to any one of these registers. Writing two bytes of data to one of these registers consists of the following sequence: Writing to multiple address registers consists of the following: 1.
AD7294 Data Sheet Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Reading the contents from any of the 8-bit registers is a single byte read operation, as shown in Figure 55. In this protocol, the first part of the transaction writes to the register pointer. When the register address has been set up, any number of reads can be performed from that particular register without having to write to the address pointer register again.
Data Sheet AD7294 MODES OF OPERATION There are two different methods of initiating a conversion on the AD7294: command mode and autocycle mode. 3. COMMAND MODE 4. In command mode, the AD7294 ADC converts on-demand on either a single channel or a sequence of channels. To enter this mode, the required combination of channels is written into the command register (0x00). The first conversion takes place at the end of this write operation, in time for the result to be read out in the next read operation.
AD7294 Data Sheet AUTOCYCLE MODE The AD7294 can be configured to convert continuously on a programmable sequence of channels making it the ideal mode of operation for system monitoring. These conversions take place in the background approximately every 50 µs, and are transparent to the master.
Data Sheet AD7294 ALERTS AND LIMITS THEORY ALERT_FLAG BIT The alert_flag bit indicates whether the conversion result being read or any other channel result has violated the limit registers associated with it. If an alert occurs and the alert_flag bit is set, the master can read the alert status register to obtain more information on where the alert occurred. ALERT STATUS REGISTERS The alert status registers are 8-bit read/write registers that provide information on an alert event.
AD7294 Data Sheet The hysteresis register can be used to avoid flicker on the ALERT/ BUSY pin. If the hysteresis function is enabled, the conversion result must return to a value of at least N LSB below the DATAHIGH register value, or N LSB above the DATALOW register value for the ALERT/BUSY output pin and alert_flag bit to be reset. The value of N is taken from the 12-bit hysteresis register associated with that channel.
Data Sheet AD7294 APPLICATIONS INFORMATION bringing considerable board area savings over alternative solutions. The AD7294 contains all the functions required for generalpurpose monitoring and control of current, voltage, and temperature. With its 59.4 V maximum common-mode range, the device is useful in industrial and automotive applications where current sensing in the presence of a high common-mode voltage is required.
AD7294 Data Sheet GAIN CONTROL OF POWER AMPLIFIER feedback loop that tracks the output of the AD8362 and adjusts the VSET input of the AD8362 accordingly. In gain control mode, a setpoint voltage, proportional in dB to the desired output power, is applied to a power detector such as the AD8362. A sample of the output power from the power amplifier (PA), through a directional coupler and attenuator (or by other means), is fed to the input of the AD8362.
Data Sheet AD7294 LAYOUT AND CONFIGURATION POWER SUPPLY BYPASSING AND GROUNDING Take the following precautions: For optimum performance, carefully consider the power supply and ground return layout on any PCB where the AD7294 is used. The PCB containing the AD7294 should have separate analog and digital sections, each having its own area of the board. The AD7294 should be located in the analog section on any PCB. • Place the remote sensing diode as close as possible to the AD7294.
AD7294 Data Sheet OUTLINE DIMENSIONS 9.20 9.00 SQ 8.80 1.20 MAX 0.75 0.60 0.45 64 49 48 1 PIN 1 7.20 7.00 SQ 6.80 TOP VIEW 0° MIN 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY SEATING PLANE (PINS DOWN) 33 32 16 17 VIEW A 0.40 BSC LEAD PITCH VIEW A 0.23 0.18 0.13 ROTATED 90° CCW 012108-A 1.05 1.00 0.95 COMPLIANT TO JEDEC STANDARDS MS-026-ABD Figure 62. 64-Lead Thin Plastic Quad Flat Package [TQFP] (SU-64-1) Dimensions shown in millimeters 8.00 BSC SQ 0.30 0.23 0.18 0.
Data Sheet AD7294 ORDERING GUIDE Model1 AD7294BSUZ AD7294BSUZRL AD7294BCPZ AD7294BCPZRL EVAL-AD7294EBZ 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 64-Lead Thin Plastic Quad Flat Package [TQFP] 64-Lead Thin Plastic Quad Flat Package [TQFP] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev.
AD7294 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05747-0-1/12(H) Rev.
