Datasheet

AD7292 Data Sheet
Rev. 0 | Page 8 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO A
GND
AND
CAN BE SOLDERED TO THE GROUND PLANE OF THE SYSTEM.
1AV
DD
2
A
GND
3
D
GND
4
DV
DD
5V
DRIVE
6
CS
7SCLK
8DIN
9DOUT
27 GPIO0/ALERT0
26 GPIO1/ALERT1
25 GPIO2/DAC DISABLE0
24 GPIO3/LDAC
23 GPIO4/DAC DISABLE1
22 GPIO5
21 GPIO6/BUSY
20 GPIO7
19 REF
OUT
10VOUT3
11VOUT2
12VOUT1 13VOUT0 14A
GND
15GPIO11 16GPIO10 17GPIO9 18GPIO8
36 REF
IN
35 VIN7 34 VIN6 33 VIN5 32 VIN4 31 VIN3 30 VIN2 29 VIN1 28 VIN0
10660-003
AD7292
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 AV
DD
Supply Pin. This pin should be decoupled to A
GND
with a 0.1 µF decoupling capacitor.
2, 14 A
GND
Analog Ground. Ground reference point for all analog circuitry on the AD7292. All analog signals should
be referred to A
GND
. Both the A
GND
and D
GND
pins should be connected to the ground plane of the system.
3 D
GND
Digital Ground. Ground reference point for all digital circuitry on the AD7292. All digital signals should be
referred to D
GND
. Both the D
GND
and A
GND
pins should be connected to the ground plane of the system.
4 DV
DD
Sets the GPIO voltage level. This pin should be decoupled to D
GND
with a 0.1 µF decoupling capacitor.
5 V
DRIVE
This pin sets the reference level of the SPI bus from 1.8 V to 5.25 V. This pin should be decoupled to D
GND
with a 0.1 µF decoupling capacitor.
6
CS
Chip Select Signal. This active low logic input signal is used to frame the serial data input.
7 SCLK SPI Clock Input.
8 DIN SPI Serial Data Input. Serial data to be loaded into the registers of the AD7292 is provided on this pin.
Data is clocked into the serial interface on the falling edge of SCLK.
9 DOUT SPI Serial Data Output. Serial data to be read from the registers of the AD7292 is provided on this pin.
Data is clocked out on the rising edge of SCLK. DOUT is high impedance when it is not outputting data.
10 to 13 VOUT3 to VOUT0 Buffered DAC Analog Outputs. Each DAC analog output is driven from an output amplifier and has a
maximum output voltage span of 5 V. Each DAC is capable of sourcing and sinking 10 mA and driving a
1 nF load.
15 to 18 GPIO11 to GPIO8 General-Purpose Input/Output Pins.
19 REF
OUT
ADC Internal Reference Output. Decouple the internal ADC reference buffer to A
GND
with a 0.1 µF
decoupling capacitor.
20 GPIO7 General-Purpose Input/Output Pin.
21 GPIO6/BUSY General-Purpose Input/Output Pin (GPIO6).
Busy Output Pin (BUSY). When a conversion starts, this output pin transitions high and remains high until
the conversion is completed.
22 GPIO5 General-Purpose Input/Output Pin.
23 GPIO4/
DAC DISABLE1
General-Purpose Input/Output Pin (GPIO4).
DAC Disable Pin 1 (DAC DISABLE1). When this pin is activated, the selected DAC outputs are disabled.
Select the DAC channels to be disabled by this pin using the GPIO4/DAC DISABLE1 subregister within the
configuration register bank (see Table 30).
24 GPIO3/LDAC General-Purpose Input/Output Pin (GPIO3).
LDAC Input Pin (LDAC). When this input is taken high, the DAC registers are updated.
25
GPIO2/
DAC DISABLE0
General-Purpose Input/Output Pin (GPIO2).
DAC Disable Pin 0 (DAC DISABLE0). When this pin is activated, the selected DAC outputs are disabled.
Select the DAC channels to be disabled by this pin using the GPIO2/DAC DISABLE0 subregister within the
configuration register bank (see Table 29).