Datasheet

AD7292 Data Sheet
Rev. 0 | Page 6 of 40
TIMING SPECIFICATIONS
AV
DD
= 4.75 V to 5.25 V, DV
DD
= 1.8 V to 5.25 V, V
REF
= 1.25 V internal, V
DRIVE
= 1.8 V to 5.25 V, A
GND
= 0 V, C
L
= 27 pF, T
A
= −40°C
to +125°C, unless otherwise noted.
1
Table 5.
Limit at T
MIN
/T
MAX
Parameter Description V
DRIVE
= 1.8 V V
DRIVE
= 2.7 V to 5.25 V Unit
t
CONVERT
ADC conversion time/BUSY high time
Temperature sensor disabled 950 950 ns max
Temperature sensor enabled 5.85 5.85 µs max
t
ACQ
ADC acquisition time 50 50 ns max
f
SCLK
Frequency of serial read clock
2
15 25 MHz max
t
1
SCLK period
66
40
ns min
t
2
SCLK low 33 20 ns min
t
3
SCLK high 33 20 ns min
t
4
CS
falling edge to SCLK rising edge 4 4 ns min
t
5
DIN setup time to SCLK falling edge 4 4 ns min
t
6
3
DIN hold time after SCLK falling edge 2 2 ns max
t
7
SCLK falling edge to
CS
rising edge 5 5 ns min
t
8
CS
high 5 5 ns min
t
9
SCLK to output data valid delay time 30 19 ns max
t
10
SCLK to output data valid hold time 7 5 ns min
t
11
4, 5
CS
rising edge to SCLK rising edge 4 4 ns max
t
12
CS
rising edge to DOUT high impedance 15 15 ns max
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DRIVE
).
2
For V
DRIVE
= 2.5 V, f
SCLK
= 22 MHz maximum.
3
Time required for the output to cross 0.2 × V
DRIVE
and 0.8 × V
DRIVE
when V
DRIVE
= 1.8 V; time required for the output to cross 0.3 × V
DRIVE
and 0.7 × V
DRIVE
when V
DRIVE
= 2.7 V to 5.25 V.
4
t
11
applies when using a continuous SCLK.
5
Guaranteed by design.
Timing Diagram
t
4
R W D5 D4 LSB
MSB MSB – 1 MSB – 2 LSB
t
3
t
9
t
2
t
5
t
6
t
7
t
8
t
11
t
10
t
1
t
12
CS
SCLK
1 2 3 4 32
DOUT
THREE-
STATE
THREE-
STATE
DIN
10660-002
Figure 2. Serial Interface Timing Diagram