Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Theory of Operation
- Serial Port Interface (SPI)
- Register Structure
- Register Descriptions
- Vendor ID Register (Address 0x00)
- ADC Data Register (Address 0x01)
- ADC Sequence Register (Address 0x03)
- Configuration Register Bank (Address 0x05)
- Digital Output Driver Subregister (Address 0x01)
- Digital I/O Function Subregister (Address 0x02)
- General Subregister (Address 0x08)
- VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11)
- ADC Sampling Mode Subregister (Address 0x12)
- VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x13 and Address 0x14)
- VIN Filter Subregister (Address 0x15)
- Conversion Delay Control Subregister (Address 0x16)
- Temperature Sensor Subregister (Address 0x20)
- Temperature Sensor Alert Routing Subregister (Address 0x21)
- GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31)
- Alert Limits Register Bank (Address 0x06)
- Alert Flags Register Bank (Address 0x07)
- Minimum and Maximum Register Bank (Address 0x08)
- Offset Register Bank (Address 0x09)
- DAC Buffer Enable Register (Address 0x0A)
- GPIO Register (Address 0x0B)
- Conversion Command Register (Address 0x0E)
- ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17)
- TSENSE Conversion Result Register (Address 0x20)
- DAC Channel Registers (Address 0x30 to Address 0x33)
- ADC Conversion Control
- DAC Output Control
- Alerts and Limits
- Outline Dimensions
AD7292 Data Sheet
Rev. 0 | Page 40 of 40
OUTLINE DIMENSIONS
1
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
36
10
18
19
27
28
9
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.23
0.18
6.10
6.00 SQ
5.90
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.70
0.60
0.40
0.25 MIN
4.05
3.90 SQ
3.85
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
03-29-2012-A
Figure 47. 36-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-36-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
AD7292BCPZ −40°C to +125°C 36-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-36-3
AD7292BCPZ-RL −40°C to +125°C 36-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-36-3
EVAL-AD7292SDZ
Evaluation Board
EVAL-SDP-CB1Z System Development Platform
1
Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10660-0-10/12(0)