Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Theory of Operation
- Serial Port Interface (SPI)
- Register Structure
- Register Descriptions
- Vendor ID Register (Address 0x00)
- ADC Data Register (Address 0x01)
- ADC Sequence Register (Address 0x03)
- Configuration Register Bank (Address 0x05)
- Digital Output Driver Subregister (Address 0x01)
- Digital I/O Function Subregister (Address 0x02)
- General Subregister (Address 0x08)
- VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11)
- ADC Sampling Mode Subregister (Address 0x12)
- VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x13 and Address 0x14)
- VIN Filter Subregister (Address 0x15)
- Conversion Delay Control Subregister (Address 0x16)
- Temperature Sensor Subregister (Address 0x20)
- Temperature Sensor Alert Routing Subregister (Address 0x21)
- GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31)
- Alert Limits Register Bank (Address 0x06)
- Alert Flags Register Bank (Address 0x07)
- Minimum and Maximum Register Bank (Address 0x08)
- Offset Register Bank (Address 0x09)
- DAC Buffer Enable Register (Address 0x0A)
- GPIO Register (Address 0x0B)
- Conversion Command Register (Address 0x0E)
- ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17)
- TSENSE Conversion Result Register (Address 0x20)
- DAC Channel Registers (Address 0x30 to Address 0x33)
- ADC Conversion Control
- DAC Output Control
- Alerts and Limits
- Outline Dimensions

AD7292 Data Sheet
Rev. 0 | Page 4 of 40
Parameter Min Typ Max Unit Test Conditions/Comments
EXTERNAL REFERENCE
Reference Input Voltage 4.75 AV
DD
V Internal reference used to calibrate
temperature sensor
Input Resistance 100 kΩ
1
Specifications also apply to differential mode.
DAC SPECIFICATIONS
AV
DD
= 4.75 V to 5.25 V, DV
DD
= 1.8 V to 5.25 V, V
REF
= 1.25 V internal, V
DRIVE
= 1.8 V to 5.25 V, A
GND
= 0 V, T
A
= −40°C to +125°C,
unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity (INL) ±0.2 ±1 LSB
Differential Nonlinearity (DNL) ±0.1 ±0.3 LSB Guaranteed monotonic
Zero-Scale Error 4.8 ±10 mV All 0s loaded to DAC register
Full-Scale Error ±0.1 ±0.5 % FS All 1s loaded to DAC register
Offset Error ±1.62 ±10 mV Measured in the linear region,
T
A
= −40°C to +125°C
Offset Error Drift ±4.4 ppm/°C Measured in the linear region, T
A
= 25°C
Gain Error ±0.35 ±0.5 % FS
Gain Error Drift ±2.6 ppm/°C
DC Power Supply Rejection Ratio (PSRR) −50 dB f
RIPPLE
up to 100 kHz
DC Crosstalk 5 μV
DAC OUTPUT CHARACTERISTICS
Output Voltage Range 0 4 × V
REF
V
Short-Circuit Current ±30 mA
Load Current ±10 mA Sink/source current; within ±200 mV
of supply
Resistive Load to A
GND
500 Ω
Capacitive Load Stability 1 nF
DC Output Impedance 1 Ω
AC CHARACTERISTICS
1
Output Voltage Settling Time 1 2 µs ¼ to ¾ scale step change within 1 LSB,
measured from last SCLK edge
Overshoot 200 mV ¼ to ¾ scale step change within 1 LSB,
measured from last SCLK edge;
C
L
= 200 pF, R
L
= 25 kΩ
Slew Rate 9 12 V/µs
Digital-to-Analog Glitch Impulse 4 nV-sec
Digital Feedthrough 0.4 nV-sec
DAC-to-DAC Crosstalk 2 nV-sec
Output Noise Spectral Density 730 nV/√Hz DAC code = midscale, 1 kHz
Output Noise 28 μV rms 0.1 Hz to 10 Hz
Output Transient Response During
Power-Up
5 mV AV
DD
ramp of 1 ms with 100 kΩ load
1
The DAC buffer output level is undefined until 30 µs after all supplies reach their minimum specified operating voltages.