Datasheet

AD7292 Data Sheet
Rev. 0 | Page 38 of 40
ALERTS AND LIMITS
ALERT LIMIT MONITORING FEATURES
The alert limits register bank comprises subregisters that set the
high and low alert limits for the eight analog input channels and
the temperature sensor channel (see Table 31). Each subregister
is 16 bits in length; values are 10-bit, left-justified (padded with
0s as the 6 LSBs). On power-up, the low limit and hysteresis sub-
registers contain all 0s, whereas the high limit subregisters are
set to 0xFFC0.
The alert high limit subregisters store the upper limit that
activates an alert. If the conversion result is greater than the value
in the alert high limit subregister, an alert is triggered. The alert
low limit subregister stores the lower limit that activates an alert.
If the conversion result is less than the value in the alert low limit
subregister, an alert is triggered.
If a conversion result exceeds the high or low limit set in the
alert limits subregister, the AD7292 signals an alert in one or
more of the following ways:
 Via hardware using the GPIO0/ALERT0 and GPIO1/
ALERT1 pins
 Via software using the alert flag bits in the conversion
result registers
 Via software using the alert bits in the alert flags register
bank
Hysteresis
The hysteresis value determines the reset point for the alert pins
and alert flags if a violation of the limits occurs. Each channel has
an associated hysteresis subregister that stores the hysteresis
value, N (see Table 31). If the hysteresis function is enabled, the
conversion result must return to a value of at least N LSB below
the alert high limit subregister value, or N LSB above the alert
low limit subregister value to reset the alert output pins and the
alert flag bits (see Figure 46).
The advantage of using the hysteresis subregister associated with
each limit subregister is that hysteresis prevents chatter on the
alert bits associated with each ADC channel and also prevents
flicker on the alert output pins. Figure 46 shows the limit check-
ing operation.
HARDWARE ALERT PINS
Pin 27 and Pin 26 (GPIO0/ALERT0 and GPIO1/ALERT1,
respectively) can be configured as alert pins (see the Digital I/O
Function Subregister (Address 0x02) section). When these pins
are configured as alert pins, they become active when the selected
conversion result exceeds the high or low limit stored in the alert
limits register bank. The polarity of the alert output pins can be
set to active high or active low via the general subregister within
the configuration register bank (see the General Subregister
(Address 0x08) section).
If an alert pin signals an alert event and the contents of the alert
flags subregisters are not read before the next conversion is com-
pleted, the contents of the subregister may change if the out-of-
range signal returns to the specified range. In this case, the ALERTx
pin no longer signals the occurrence of an alert event.
ALERT FLAG BITS IN THE CONVERSION RESULT
REGISTERS
The T
SENSE
alert and ADC alert flag bits in the ADC conversion
result and T
SENSE
conversion result registers indicate whether the
conversion result being read or any other channel result has
violated the limit registers associated with it. If an alert occurs
and the alert bit is set in a conversion result register, the master
can read the alert flags register bank to obtain more information
about where the alert occurred.
HIGH LIMIT
LOW LIMIT
HIGH LIMIT – HYSTERESIS
LOW LIMIT + HYSTERESIS
TIME
INPUT SIGNAL
ALERT SIGNAL
10660-052
Figure 46. Limit Checking: Alert High Limit, Alert Low Limit, and Hysteresis