Datasheet

Data Sheet AD7292
Rev. 0 | Page 37 of 40
DAC OUTPUT CONTROL
To s et the DAC output voltage codes, the user must write to the
DAC channel registers (Address 0x30 to Address 0x33). Figure 44
shows an example of how to set the DAC output voltage codes.
1. The DAC buffer enable register (Address 0x0A) is pointed
to with the write bit set.
2. The following two bytes specify which of the four DAC
output buffers are enabled.
3. The DAC channel register (DAC Channel 0 register in
Figure 44) is pointed to with the write bit set.
4. The following two bytes contain the value to be written to
the DAC channel.
On completion of this write, the DAC channel output is imme-
diately updated to the new value, provided that the
LDAC
bit in
the DAC channel register is not set.
Note that the process can be reversed—that is, the user can first
write a value to the DAC channel register and then enable the
DAC output buffer.
LDAC OPERATION
A write to a DAC channel register (Address 0x30 to Address 0x33)
is addressed to the DAC input register; a read from a DAC channel
register is addressed to the DAC output register (see Figure 45).
The DAC output registers are updated based on the
LDAC
bit in
the DAC channel register or on the polarity of the GPIO3/LDAC
pin (if the pin is configured as an LDAC pin).
When the
LDAC
bit in the DAC channel register is set to 1, the
10-bit DAC value is stored, but the DAC channel output is not
updated. When a write to any DAC channel register occurs with
the
LDAC
bit cleared, all DAC channel outputs are updated with
the stored values from previous writes.
When the
LDAC
bit in the DAC channel register is used to control
the updating of the DAC output, the LDAC pin function should
be disabled, that is, the GPIO3/LDAC pin should be configured
as GPIO3.
The GPIO3/LDAC pin can be used to update the DAC outputs
with the stored values when the pin is configured as an LDAC
pin (see the Digital Output Driver Subregister (Address 0x01)
section and the Digital I/O Function Subregister (Address 0x02)
section). If the GPIO3/LDAC pin is configured as an LDAC
input and is taken high, the DAC output registers are updated;
conversely, if this input pin is held low, the DAC value is stored
but the channel output is not updated.
SIMULTANEOUS UPDATE OF ALL DAC OUTPUTS
It may be useful to update all four DAC channel registers
simultaneously with the same value but not update the DAC
outputs (
LDAC
bit is set to 1; LDAC pin is set to 0). Setting
the copy bit (Bit 1) when writing to any DAC channel register
instructs the AD7292 to copy the new DAC value to all the DAC
input registers.
CS
SCLK
DIN
POINT TO DAC
BUFFER ENABLE
REGISTER
POINT TO DAC
CHANNEL 0
REGISTER
WRITE TO DAC
BUFFER ENABLE REGISTER [D15:D0]
WRITE TO DAC
CHANNEL 0 REGISTER [D15:D0]
1
8
24 48
32
10660-050
Figure 44. Setting the DAC Output Voltage Code
DAC INPUT REGISTER
DAC CHANNEL REGISTER (0x30 TO 0x33)
READ
WRITE
SCLK
LDAC BIT
GPIO3/LDAC PIN
1
1
PROVIDED THE GPIO3/LDAC PIN IS CONFIGUREDAS AN LDAC PIN.
DAC OUTPUT REGISTER
DAC VOUTx
10660-051
Figure 45. DAC Input and Output Registers