Datasheet

Data Sheet AD7292
Rev. 0 | Page 35 of 40
ADC CONVERSION CONTROL
ADC CONVERSION COMMAND
To initiate an ADC conversion on a channel, the conversion
command must be written to the AD7292. The special address
pointer byte, 0x8E, consists of the conversion command register
(Address 0x0E) with the MSB read bit set to 1 to signify an
ADC conversion. When the conversion command is received,
the AD7292 uses the current value of the address pointer to
determine which channel to convert on.
In Figure 40, the first byte sets the address pointer with both the
read and write bits cleared and sets Bits[D5:D0] to point to the
selected channel conversion result register. The second byte con-
tains the conversion command with the read bit set. After receiving
the conversion command, the AD7292 stays in conversion mode,
performing a new ADC conversion at the end of each read, until
the
CS
(chip select) input signal is taken high.
In Figure 41, the address pointer is set to point to the ADC data
register (Address 0x01) with both the read and write bits cleared.
The conversion command is issued, and the contents of the ADC
sequence register specify the sequence of ADC channels for
conversion (see the ADC Sequencer section).
In this example, the ADC sequence register is programmed to
convert on analog input channels VIN0 and VIN1. The AD7292
stays in conversion mode and performs a new ADC conversion
at the end of each read until the
CS
input signal is taken high.
In the examples shown in Figure 40 and Figure 41, an SCLK
delay is inserted following the conversion command to allow
the ADC to perform the conversion before the data is read. If
temperature sensor conversions are requested, a longer delay
is necessary (see the Temperature Sensor section).
In some applications, the SPI bus master may not allow the
serial clock to be held low during a read sequence, and it may
be necessary to take
CS
high, as shown in Figure 42. In this
case, the
CS
line must remain low while the ADC conversion is
in progress to prevent possible corruption of the ADC result.
In the example shown in Figure 42, the address pointer is set
to point to the ADC data register (Address 0x01) with both the
read and write bits cleared. The conversion command is issued
with the read bit set. The
CS
line is taken high after the conver-
sion on VIN0 is completed. The
CS
line is then brought low,
and the ADC data register is pointed to with the read bit set.
The conversion result is clocked out. The conversion command
is reissued before the
CS
line is taken high again, and so on.
CS
SCLK
DIN
DOUT
1 16 1 16 1 16
POINT TO CHANNEL
FOR CONVERSION
CONVERSION RESULT FOR
SELECTED CHANNEL [D15:D0]
BUSY
CONVERSION RESULT FOR
SELECTED CHANNEL [D15:D0]
CONVERT
SELECTED
CHANNEL
CONVERT
SELECTED
CHANNEL
CONVERT
SELECTED
CHANNEL
ISSUE CONVERSION
COMMAND
8
10660-046
Figure 40. ADC Conversion Command (ADC Sequencer Not Used)
CS
SCLK
DIN
DOUT
1 16 1 8 16
POINT TO ADC
DATA REGISTER
VIN0 RESULT
[D15:D0]
VIN1 RESULT
[D15:D0]
BUSY
CONVERT
VIN0
CONVERT
VIN1
CONVERT
VIN0
ISSUE CONVERSION
COMMAND
8
1 16
8
10660-047
Figure 41. ADC Conversion Command (ADC Sequencer Used)