Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Theory of Operation
- Serial Port Interface (SPI)
- Register Structure
- Register Descriptions
- Vendor ID Register (Address 0x00)
- ADC Data Register (Address 0x01)
- ADC Sequence Register (Address 0x03)
- Configuration Register Bank (Address 0x05)
- Digital Output Driver Subregister (Address 0x01)
- Digital I/O Function Subregister (Address 0x02)
- General Subregister (Address 0x08)
- VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11)
- ADC Sampling Mode Subregister (Address 0x12)
- VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x13 and Address 0x14)
- VIN Filter Subregister (Address 0x15)
- Conversion Delay Control Subregister (Address 0x16)
- Temperature Sensor Subregister (Address 0x20)
- Temperature Sensor Alert Routing Subregister (Address 0x21)
- GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31)
- Alert Limits Register Bank (Address 0x06)
- Alert Flags Register Bank (Address 0x07)
- Minimum and Maximum Register Bank (Address 0x08)
- Offset Register Bank (Address 0x09)
- DAC Buffer Enable Register (Address 0x0A)
- GPIO Register (Address 0x0B)
- Conversion Command Register (Address 0x0E)
- ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17)
- TSENSE Conversion Result Register (Address 0x20)
- DAC Channel Registers (Address 0x30 to Address 0x33)
- ADC Conversion Control
- DAC Output Control
- Alerts and Limits
- Outline Dimensions

Data Sheet AD7292
Rev. 0 | Page 31 of 40
ALERT FLAGS REGISTER BANK (ADDRESS 0x07)
If a conversion result activates an alert (as specified in the alert
limits register bank), the alert flags register bank can be read
to obtain more information about the alert. This register bank
contains the ADC alert flags and T
SENSE
alert flags subregisters.
Both subregisters store flags that are triggered when the mini-
mum or maximum conversion limits, as defined in the alert
limits register bank, are exceeded.
Table 32. Alert Flags Register Bank Subregisters
1
Bits in the alert flags subregisters can be reset by writing 1 to the selected bits.
ADC Alert Flags and T
SENSE
Alert Flags Subregisters
(Address 0x00 and Address 0x02)
The ADC alert flags subregister stores alerts for the analog volt-
age conversion channels, VIN0 to VIN7. The T
SENSE
alert flags
subregister stores alerts for the temperature sensor channel.
These subregisters contain two status bits per channel: one
corresponding to the high limit, and the other corresponding to
the low limit. A bit with a status of 1 shows the channel on which
the violation occurred and whether the violation occurred on the
high or low limit.
If additional alert events occur on any other channels after the
first alert is triggered but before the alert flags subregister is read,
the corresponding bits for the new alert events are also set. For
example, if Bit D14 in the ADC alert flags subregister is set to 1,
the low limit on Channel 7 has been exceeded, whereas if Bit D3
is set to 1, the high limit on Channel 1 has been exceeded.
To find out which channel or channels caused the alert flag, the
user must read the ADC alert flags subregister or the T
SENSE
alert
flags subregister. If the ADC alert flags subregister or the T
SENSE
alert flags subregister is accessed with both the read and write bits
of the address pointer set to 1, the stored alert flags can be read
and reset in one operation. A blanket reset can be performed by
writing 0xFFFF to the ADC alert flags subregister, or 0x0003 to
the T
SENSE
alert flags subregister, thus clearing all alert flags.
Table 33. ADC Alert Flags Subregister, Bit Function Descriptions
Bits Bit Name R/W Description
D15 VIN7 high limit flag R/W 1 = VIN7 high limit exceeded
D14 VIN7 low limit flag R/W 1 = VIN7 low limit exceeded
D13 VIN6 high limit flag R/W 1 = VIN6 high limit exceeded
D12 VIN6 low limit flag R/W 1 = VIN6 low limit exceeded
D11 VIN5 high limit flag R/W 1 = VIN5 high limit exceeded
D10 VIN5 low limit flag R/W 1 = VIN5 low limit exceeded
D9 VIN4 high limit flag R/W 1 = VIN4 high limit exceeded
D8 VIN4 low limit flag R/W 1 = VIN4 low limit exceeded
D7 VIN3 high limit flag R/W 1 = VIN3 high limit exceeded
D6 VIN3 low limit flag R/W 1 = VIN3 low limit exceeded
D5 VIN2 high limit flag R/W 1 = VIN2 high limit exceeded
D4 VIN2 low limit flag R/W 1 = VIN2 low limit exceeded
D3 VIN1 high limit flag R/W 1 = VIN1 high limit exceeded
D2 VIN1 low limit flag R/W 1 = VIN1 low limit exceeded
D1 VIN0 high limit flag R/W 1 = VIN0 high limit exceeded
D0 VIN0 low limit flag R/W 1 = VIN0 low limit exceeded
Table 34. T
SENSE
Alert Flags Subregister, Bit Function Descriptions
Bits Bit Name R/W Description
[D15:D2] Reserved R/W Reserved
D1 T
SENSE
high limit flag R/W 1 = T
SENSE
high limit exceeded
D0 T
SENSE
low limit flag R/W 1 = T
SENSE
low limit exceeded
Subaddress (Hex) Subregister Name
1
0x00 ADC alert flags subregister
0x01 Reserved
0x02 T
SENSE
alert flags subregister
0x03 to 0xFF Reserved