Datasheet

AD7292 Data Sheet
Rev. 0 | Page 30 of 40
ALERT LIMITS REGISTER BANK (ADDRESS 0x06)
The alert limits register bank comprises subregisters that set the
high and low alert limits for the eight analog input channels and
the temperature sensor channel (see Table 31). Each subregister
is 16 bits in length; values are 10-bit, left-justified (padded with
0s as the 6 LSBs). On power-up, the low limit and hysteresis
subregisters contain all 0s, whereas the high limit subregisters
are set to 0xFFC0.
If a conversion result exceeds the high or low limit set in the
alert limits subregister, the AD7292 signals an alert in one or
more of the following ways:
• Via hardware using the GPIO0/ALERT0 and GPIO1/ALERT1
pins (see the Hardware Alert Pins section)
• Via software using the alert flag bits in the conversion result
registers (see the ADC Conversion Result Registers, VIN0
to VIN7 (Address 0x10 to Address 0x17) section and the
T
SENSE
Conversion Result Register (Address 0x20) section)
• Via software using the alert bits in the alert flags register
bank (see the Alert Flags Register Bank (Address 0x07)
section)
Alert High Limit and Alert Low Limit Subregisters
The alert high limit subregisters store the upper limit that
activates an alert. If the conversion result is greater than the value
in the alert high limit subregister, an alert is triggered. The alert
low limit subregister stores the lower limit that activates an alert.
If the conversion result is less than the value in the alert low limit
subregister, an alert is triggered.
An alert associated with either the alert high limit or alert low
limit subregister is cleared automatically after the monitored
signal is back in range, that is, when the conversion result returns
between the configured high and low limits. The contents of the
alert flags subregisters are updated after each conversion (see the
Alert Flags Register Bank (Address 0x07) section).
Hysteresis Subregisters
Each channel has an associated hysteresis subregister that stores
the hysteresis value, N (see Table 31). The hysteresis subregisters
can be used to avoid flicker on the GPIO0/ALERT0 and GPIO1/
ALERT1 pins. If the hysteresis function is enabled, the conversion
result must return to a value of at least N LSB below the alert high
limit subregister value, or N LSB above the alert low limit sub-
register value for the alert output pins and alert flag bits to be reset
(see Figure 46). The value of N is taken from the 10 MSBs of the
16-bit, read/write hysteresis subregister. For more information,
see the Hysteresis section.
Table 31. Alert Limits Register Bank Subregisters
1
All subregisters in the alert limits register bank are read/write.
Subaddress (Hex) Subregister Name
1
0x00 VIN0 alert high limit
0x01 VIN0 alert low limit
0x02 VIN0 hysteresis
0x03
VIN1 alert high limit
0x04 VIN1 alert low limit
0x05 VIN1 hysteresis
0x06 VIN2 alert high limit
0x07 VIN2 alert low limit
0x08 VIN2 hysteresis
0x09 VIN3 alert high limit
0x0A VIN3 alert low limit
0x0B VIN3 hysteresis
0x0C VIN4 alert high limit
0x0D VIN4 alert low limit
0x0E VIN4 hysteresis
0x0F VIN5 alert high limit
0x10 VIN5 alert low limit
0x11 VIN5 hysteresis
0x12 VIN6 alert high limit
0x13 VIN6 alert low limit
0x14
VIN6 hysteresis
0x15 VIN7 alert high limit
0x16 VIN7 alert low limit
0x17 VIN7 hysteresis
0x18 to 0x2F Reserved
0x30 T
SENSE
alert high limit
0x31 T
SENSE
alert low limit
0x32 T
SENSE
hysteresis
0x33 to 0xFF Reserved