Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Theory of Operation
- Serial Port Interface (SPI)
- Register Structure
- Register Descriptions
- Vendor ID Register (Address 0x00)
- ADC Data Register (Address 0x01)
- ADC Sequence Register (Address 0x03)
- Configuration Register Bank (Address 0x05)
- Digital Output Driver Subregister (Address 0x01)
- Digital I/O Function Subregister (Address 0x02)
- General Subregister (Address 0x08)
- VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11)
- ADC Sampling Mode Subregister (Address 0x12)
- VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x13 and Address 0x14)
- VIN Filter Subregister (Address 0x15)
- Conversion Delay Control Subregister (Address 0x16)
- Temperature Sensor Subregister (Address 0x20)
- Temperature Sensor Alert Routing Subregister (Address 0x21)
- GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31)
- Alert Limits Register Bank (Address 0x06)
- Alert Flags Register Bank (Address 0x07)
- Minimum and Maximum Register Bank (Address 0x08)
- Offset Register Bank (Address 0x09)
- DAC Buffer Enable Register (Address 0x0A)
- GPIO Register (Address 0x0B)
- Conversion Command Register (Address 0x0E)
- ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17)
- TSENSE Conversion Result Register (Address 0x20)
- DAC Channel Registers (Address 0x30 to Address 0x33)
- ADC Conversion Control
- DAC Output Control
- Alerts and Limits
- Outline Dimensions
Data Sheet AD7292
Rev. 0 | Page 29 of 40
GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1
Subregisters (Address 0x30 and Address 0x31)
The 16-bit, read/write GPIO2/DAC DISABLE0 and GPIO4/DAC
DISABLE1 subregisters specify which DAC channels are disabled
by the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins.
For example, when Bit D0 in the GPIO2/DAC DISABLE0 sub-
register is set to 1, the GPIO2/DAC DISABLE0 pin disables DAC
output VOUT0 when the pin is taken high. On power-up, these
subregisters contain all 0s by default.
For information about how to enable the DAC disable function
on the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1
pins, see the Digital Output Driver Subregister (Address 0x01)
section and the Digital I/O Function Subregister (Address 0x02)
section.
Table 29. GPIO2/DAC DISABLE0 Subregister, Bit Function Descriptions
Bits Bit Name R/W Description
[D15:D4] Reserved R/W Reserved.
D3 Disable VOUT3 pin R/W This bit specifies whether the VOUT3 output is disabled when the GPIO2/DAC DISABLE0
pin is high.
0 = disable control of VOUT3 by the GPIO2/DAC DISABLE0 pin (default).
1 = enable control of VOUT3 by the GPIO2/DAC DISABLE0 pin.
D2 Disable VOUT2 pin R/W This bit specifies whether the VOUT2 output is disabled when the GPIO2/DAC DISABLE0
pin is high.
0 = disable control of VOUT2 by the GPIO2/DAC DISABLE0 pin (default).
1 = enable control of VOUT2 by the GPIO2/DAC DISABLE0 pin.
D1 Disable VOUT1 pin R/W This bit specifies whether the VOUT1 output is disabled when the GPIO2/DAC DISABLE0
pin is high.
0 = disable control of VOUT1 by the GPIO2/DAC DISABLE0 pin (default).
1 = enable control of VOUT1 by the GPIO2/DAC DISABLE0 pin.
D0 Disable VOUT0 pin R/W This bit specifies whether the VOUT0 output is disabled when the GPIO2/DAC DISABLE0
pin is high.
0 = disable control of VOUT0 by the GPIO2/DAC DISABLE0 pin (default).
1 = enable control of VOUT0 by the GPIO2/DAC DISABLE0 pin.
Table 30. GPIO4/DAC DISABLE1 Subregister, Bit Function Descriptions
Bits Bit Name R/W Description
[D15:D4] Reserved R/W Reserved.
D3
Disable VOUT3 pin
R/W
This bit specifies whether the VOUT3 output is disabled when the GPIO4/DAC DISABLE1
pin is high.
0 = disable control of VOUT3 by the GPIO4/DAC DISABLE1 pin (default).
1 = enable control of VOUT3 by the GPIO4/DAC DISABLE1 pin.
D2 Disable VOUT2 pin R/W This bit specifies whether the VOUT2 output is disabled when the GPIO4/DAC DISABLE1
pin is high.
0 = disable control of VOUT2 by the GPIO4/DAC DISABLE1 pin (default).
1 = enable control of VOUT2 by the GPIO4/DAC DISABLE1 pin.
D1 Disable VOUT1 pin R/W This bit specifies whether the VOUT1 output is disabled when the GPIO4/DAC DISABLE1
pin is high.
0 = disable control of VOUT1 by the GPIO4/DAC DISABLE1 pin (default).
1 = enable control of VOUT1 by the GPIO4/DAC DISABLE1 pin.
D0 Disable VOUT0 pin R/W This bit specifies whether the VOUT0 output is disabled when the GPIO4/DAC DISABLE1
pin is high.
0 = disable control of VOUT0 by the GPIO4/DAC DISABLE1 pin (default).
1 = enable control of VOUT0 by the GPIO4/DAC DISABLE1 pin.