Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Theory of Operation
- Serial Port Interface (SPI)
- Register Structure
- Register Descriptions
- Vendor ID Register (Address 0x00)
- ADC Data Register (Address 0x01)
- ADC Sequence Register (Address 0x03)
- Configuration Register Bank (Address 0x05)
- Digital Output Driver Subregister (Address 0x01)
- Digital I/O Function Subregister (Address 0x02)
- General Subregister (Address 0x08)
- VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11)
- ADC Sampling Mode Subregister (Address 0x12)
- VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x13 and Address 0x14)
- VIN Filter Subregister (Address 0x15)
- Conversion Delay Control Subregister (Address 0x16)
- Temperature Sensor Subregister (Address 0x20)
- Temperature Sensor Alert Routing Subregister (Address 0x21)
- GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31)
- Alert Limits Register Bank (Address 0x06)
- Alert Flags Register Bank (Address 0x07)
- Minimum and Maximum Register Bank (Address 0x08)
- Offset Register Bank (Address 0x09)
- DAC Buffer Enable Register (Address 0x0A)
- GPIO Register (Address 0x0B)
- Conversion Command Register (Address 0x0E)
- ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17)
- TSENSE Conversion Result Register (Address 0x20)
- DAC Channel Registers (Address 0x30 to Address 0x33)
- ADC Conversion Control
- DAC Output Control
- Alerts and Limits
- Outline Dimensions
Data Sheet AD7292
Rev. 0 | Page 25 of 40
ADC Sampling Mode Subregister (Address 0x12)
Table 22 lists the bit function descriptions for the 16-bit ADC
sampling mode subregister. Bit D0 allows the user to enable
differential input mode for analog input channels VIN0 and
VIN1. When enabled and converting on VIN0, the differential
input to the ADC is (VIN0, VIN1). When enabled and convert-
ing on VIN1, the differential input to the ADC is (VIN1, VIN0).
To use differential mode, Bit D0 must be set to 1.
Bits[D15:D8] specify whether the corresponding analog input,
VIN7 to VIN0, is measured with respect to AV
DD
or A
GND
.
Table 22. ADC Sampling Mode Subregister, Bit Function Descriptions (Default = 0)
Bits Bit Name R/W Description
D15 VIN7 sampling mode R/W This bit specifies whether VIN7 is measured with respect to AV
DD
or A
GND
.
0 = sample with respect to AV
DD
.
1 = sample with respect to A
GND
.
D14 VIN6 sampling mode R/W This bit specifies whether VIN6 is measured with respect to AV
DD
or A
GND
.
0 = sample with respect to AV
DD
.
1 = sample with respect to A
GND
.
D13 VIN5 sampling mode R/W This bit specifies whether VIN5 is measured with respect to AV
DD
or A
GND
.
0 = sample with respect to AV
DD
.
1 = sample with respect to A
GND
.
D12 VIN4 sampling mode R/W This bit specifies whether VIN4 is measured with respect to AV
DD
or A
GND
.
0 = sample with respect to AV
DD
.
1 = sample with respect to A
GND
.
D11 VIN3 sampling mode R/W This bit specifies whether VIN3 is measured with respect to AV
DD
or A
GND
.
0 = sample with respect to AV
DD
.
1 = sample with respect to A
GND
.
D10 VIN2 sampling mode R/W This bit specifies whether VIN2 is measured with respect to AV
DD
or A
GND
.
0 = sample with respect to AV
DD
.
1 = sample with respect to A
GND
.
D9 VIN1 sampling mode R/W This bit specifies whether VIN1 is measured with respect to AV
DD
or A
GND
.
0 = sample with respect to AV
DD
.
1 = sample with respect to A
GND
.
D8 VIN0 sampling mode R/W This bit specifies whether VIN0 is measured with respect to AV
DD
or A
GND
.
0 = sample with respect to AV
DD
.
1 = sample with respect to A
GND
.
[D7:D1] Reserved R/W Reserved.
D0 VIN0/VIN1 differential
mode
R/W This bit specifies whether VIN0 and VIN1 function as two single-ended inputs or as a
differential pair.
0 = single-ended mode.
1 = differential mode.