Datasheet

AD7292 Data Sheet
Rev. 0 | Page 24 of 40
VIN RANGE0 and VIN RANGE1 Subregisters
(Address 0x10 and Address 0x11)
The 16-bit VIN RANGE0 and VIN RANGE1 subregisters
specify a divide-by-2 factor for each analog input channel,
VIN0 to VIN7. A divide-by-2 factor from both the VIN
RANGE0 and VIN RANGE1 subregisters can be applied to
each channel; that is, setting Bit D0 of VIN RANGE1 and Bit D0
of VIN RANGE0 enables a divide-by-4 factor for the VIN0 input
range. The settings of the VIN RANGE0 and VIN RANGE1 bits
are ignored if samples are with respect to AV
DD
(see the ADC
Sampling Mode Subregister (Address 0x12) section).
Table 20. VIN RANGE0 and VIN RANGE1 Subregisters, Bit Function Descriptions (Default = 0)
Bits Bit Name R/W Description
[D15:D8] Reserved R/W Reserved
D7 VIN7 range R/W Analog input range for VIN7 (see Table 21)
D6 VIN6 range R/W Analog input range for VIN6 (see Table 21)
D5 VIN5 range R/W Analog input range for VIN5 (see Table 21)
D4 VIN4 range R/W Analog input range for VIN4 (see Table 21)
D3
VIN3 range
R/W
Analog input range for VIN3 (see Table 21)
D2 VIN2 range R/W Analog input range for VIN2 (see Table 21)
D1 VIN1 range R/W Analog input range for VIN1 (see Table 21)
D0 VIN0 range R/W Analog input range for VIN0 (see Table 21)
Table 21. Analog Input Range Selection
Sample with Respect to A
GND
Sample with Respect to AV
DD
Subregister Bit Settings Single-Ended Input Range Differential Input Range Single-Ended Input Range
VIN RANGE1 VIN RANGE0 (VIN0 to VIN7) (VIN0 and VIN1 Only) (VIN0 to VIN7)
0 0 0 V to 4 × V
REF
−4 × V
REF
to +4 × V
REF
(AV
DD
− 4 × V
REF
) to AV
DD
0 1 0 V to 2 × V
REF
−2 × V
REF
to +2 × V
REF
Not applicable
1 0 0 V to 2 × V
REF
−2 × V
REF
to +2 × V
REF
Not applicable
1 1 0 V to V
REF
−V
REF
to +V
REF
Not applicable