Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Theory of Operation
- Serial Port Interface (SPI)
- Register Structure
- Register Descriptions
- Vendor ID Register (Address 0x00)
- ADC Data Register (Address 0x01)
- ADC Sequence Register (Address 0x03)
- Configuration Register Bank (Address 0x05)
- Digital Output Driver Subregister (Address 0x01)
- Digital I/O Function Subregister (Address 0x02)
- General Subregister (Address 0x08)
- VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11)
- ADC Sampling Mode Subregister (Address 0x12)
- VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x13 and Address 0x14)
- VIN Filter Subregister (Address 0x15)
- Conversion Delay Control Subregister (Address 0x16)
- Temperature Sensor Subregister (Address 0x20)
- Temperature Sensor Alert Routing Subregister (Address 0x21)
- GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31)
- Alert Limits Register Bank (Address 0x06)
- Alert Flags Register Bank (Address 0x07)
- Minimum and Maximum Register Bank (Address 0x08)
- Offset Register Bank (Address 0x09)
- DAC Buffer Enable Register (Address 0x0A)
- GPIO Register (Address 0x0B)
- Conversion Command Register (Address 0x0E)
- ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17)
- TSENSE Conversion Result Register (Address 0x20)
- DAC Channel Registers (Address 0x30 to Address 0x33)
- ADC Conversion Control
- DAC Output Control
- Alerts and Limits
- Outline Dimensions
Data Sheet AD7292
Rev. 0 | Page 23 of 40
General Subregister (Address 0x08)
When the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1
pins are configured as DAC disable pins (via the digital I/O func-
tion subregister), Bits[D2:D1] of the 16-bit general subregister
control the power disable mode of these two pins. Table 19 shows
the four power disable modes. The GPIO2/DAC DISABLE0 and
GPIO4/DAC DISABLE1 subregisters determine which DAC out-
puts are controlled by the GPIO2/DAC DISABLE0 and GPIO4/
DAC DISABLE1 pins (see Table 29 and Table 30).
Bit D5 and Bit D4 of the general subregister are used to configure
the polarity of the ALERT output pins when the GPIO1/ALERT1
and GPIO0/ALERT0 pins are configured as alert outputs (see the
Digital Output Driver Subregister (Address 0x01) section and
the Digital I/O Function Subregister (Address 0x02) section).
Bit D8 is used to select the source of the voltage reference used
for the AD7292. When this bit is set to 1, the external reference
is used. When this bit is set to 0, the internal reference is used.
Table 19. General Subregister, Bit Function Descriptions
Bits Bit Name R/W Description
[D15:D9] Reserved R/W Reserved.
D8 Reference mode R/W This bit specifies whether the internal reference or an external reference is used.
0 = internal reference used (default).
1 = external reference used.
[D7:D6] Reserved R/W Reserved.
D5 ALERT1 polarity R/W When the GPIO1/ALERT1 pin is configured to function as an alert, this bit sets the polarity
of the ALERT1 pin.
0 = active low (default).
1 = active high.
D4 ALERT0 polarity R/W When the GPIO0/ALERT0 pin is configured to function as an alert, this bit sets the polarity
of the ALERT0 pin.
0 = active low (default).
1 = active high.
D3 Reserved R/W Reserved.
[D2:D1] DAC disable mode R/W These bits control the disable mode of the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1
pins when these pins are configured to function as DAC disable pins.
00 = 1 kΩ and 100 kΩ resistors in parallel to ground (default).
01 = 100 kΩ resistor to ground.
10 = 1 kΩ resistor to ground.
11 = high impedance.
D0 Reserved R/W Reserved.