Datasheet

Data Sheet AD7292
Rev. 0 | Page 21 of 40
REGISTER DESCRIPTIONS
VENDOR ID REGISTER (ADDRESS 0x00)
The 16-bit, read-only vendor ID register stores the Analog
Devices vendor ID, 0x0018. The vendor ID register is provided
to identify the AD7292 to an SPI master such as a microcontroller.
ADC DATA REGISTER (ADDRESS 0x01)
The 16-bit, read-only ADC data register provides read access to
the most recent ADC conversion result. This register provides
10 bits of conversion data, four channel identifier bits, and two
alert bits (see the ADC Conversion Control section).
ADC SEQUENCE REGISTER (ADDRESS 0x03)
The 16-bit, read/write ADC sequence register allows the user to
specify a preprogrammed sequence of ADC channels for conver-
sion. The ADC converts on each of the specified ADC channels
in turn. For more information, see the ADC Conversion Control
section. Table 16 describes the register bit functions. Bit D15 is
the first bit in the data stream. On power-up, the ADC sequence
register contains all 0s by default.
Temperature sensor results can be inserted into the sequence by
writing a 1 to Bit D8 of the ADC sequence register, provided that
the temperature sensor has been enabled in the temperature
sensor subregister within the configuration register bank (see
the Temperature Sensor Subregister (Address 0x20) section).
CONFIGURATION REGISTER BANK (ADDRESS 0x05)
The configuration register bank subregisters are listed in Table 15.
On power-up, the subregisters within the configuration register
bank contain all 0s by default.
Table 15. Configuration Register Bank Subregisters
Subaddress (Hex)
Subregister Name
1
0x01 Digital output driver
0x02
Digital I/O function
0x08 General
0x10 VIN RANGE0
0x11 VIN RANGE1
0x12 ADC sampling mode
0x13 VIN ALERT0 routing
0x14 VIN ALERT1 routing
0x15 VIN filter
0x16 Conversion delay control
0x20 Temperature sensor
0x21 Temperature sensor alert routing
0x30 GPIO2/DAC DISABLE0
0x31 GPIO4/DAC DISABLE1
1
All subregisters in the configuration register bank are read/write.
Table 16. ADC Sequence Register, Bit Function Descriptions
Bits Bit Name R/W Description
[D15:D9] Reserved R/W Reserved
D8 T
SENSE
readback enable R/W 0 = disable T
SENSE
readback
1 = enable T
SENSE
readback
D7 ADC Channel 7 convert R/W 0 = disable conversion of Channel 7
1 = enable conversion of Channel 7
D6 ADC Channel 6 convert R/W 0 = disable conversion of Channel 6
1 = enable conversion of Channel 6
D5 ADC Channel 5 convert R/W 0 = disable conversion of Channel 5
1 = enable conversion of Channel 5
D4 ADC Channel 4 convert R/W 0 = disable conversion of Channel 4
1 = enable conversion of Channel 4
D3 ADC Channel 3 convert R/W 0 = disable conversion of Channel 3
1 = enable conversion of Channel 3
D2 ADC Channel 2 convert R/W 0 = disable conversion of Channel 2
1 = enable conversion of Channel 2
D1 ADC Channel 1 convert R/W 0 = disable conversion of Channel 1
1 = enable conversion of Channel 1
D0 ADC Channel 0 convert R/W 0 = disable conversion of Channel 0
1 = enable conversion of Channel 0