Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Theory of Operation
- Serial Port Interface (SPI)
- Register Structure
- Register Descriptions
- Vendor ID Register (Address 0x00)
- ADC Data Register (Address 0x01)
- ADC Sequence Register (Address 0x03)
- Configuration Register Bank (Address 0x05)
- Digital Output Driver Subregister (Address 0x01)
- Digital I/O Function Subregister (Address 0x02)
- General Subregister (Address 0x08)
- VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11)
- ADC Sampling Mode Subregister (Address 0x12)
- VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x13 and Address 0x14)
- VIN Filter Subregister (Address 0x15)
- Conversion Delay Control Subregister (Address 0x16)
- Temperature Sensor Subregister (Address 0x20)
- Temperature Sensor Alert Routing Subregister (Address 0x21)
- GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31)
- Alert Limits Register Bank (Address 0x06)
- Alert Flags Register Bank (Address 0x07)
- Minimum and Maximum Register Bank (Address 0x08)
- Offset Register Bank (Address 0x09)
- DAC Buffer Enable Register (Address 0x0A)
- GPIO Register (Address 0x0B)
- Conversion Command Register (Address 0x0E)
- ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17)
- TSENSE Conversion Result Register (Address 0x20)
- DAC Channel Registers (Address 0x30 to Address 0x33)
- ADC Conversion Control
- DAC Output Control
- Alerts and Limits
- Outline Dimensions

AD7292 Data Sheet
Rev. 0 | Page 18 of 40
SERIAL PORT INTERFACE (SPI)
The AD7292 serial port interface (SPI) allows the user to
configure the device for specific functions and operations
through an internal structured register space. The interface
consists of four signals:
CS
, SCLK, DIN, and DOUT. The SPI
reference level is set by Pin 5 (V
DRIVE
) to a level in the range of
1.8 V to 5.25 V.
SCLK is the serial clock input for the device; all data transfers
on DIN or DOUT take place with respect to SCLK. The chip
select input pin (
CS
) is an active low control that initiates the
data transfer and conversion process.
Data is clocked into the AD7292 on the SCLK falling edge.
Data is loaded into the device MSB first. The length of each
frame can vary and depends on the command being sent. Data
is clocked out of the AD7292 on DOUT in the same frame as
the read command, on the rising edge of SCLK while
CS
is low.
When
CS
is high, the SCLK and DIN signals are ignored and
the DOUT line becomes high impedance.
INTERFACE PROTOCOL
When reading from or writing to the AD7292, the first byte con-
tains the address pointer (see Table 13). Bit D7 and Bit D6 of the
address pointer are the read and write bits, respectively. Bit D5 to
Bit D0 of the address pointer specify the register address for the
read or write operation. A register can be simultaneously read
from and written to by setting both Bit D7 and Bit D6 to 1.
Table 13. Address Pointer
D7
D6
D5
D4
D3
D2
D1
D0
R W Register select
After the address pointer, subsequent data for writing to the part
is supplied in bytes (see Figure 36). Some registers are located
within register banks and, therefore, require both a pointer address
and a subpointer address. The subpointer address is specified
in the first byte following the pointer address (see Figure 37).
Figure 36 through Figure 38 show the read and write data formats.
These figures show read operations; for a write to a register or
subregister, the write bit is set and the DOUT line remains high
impedance.
If neither the read nor write bit is set (Bit D7 and Bit D6 of the
address pointer are set to 0), the address pointer is updated but
no data is read or written. Note that writing this command also
reinitializes the ADC sequencer (see the ADC Conversion
Control section).
On completion of a read or write, the AD7292 is ready to accept
a new pointer address; alternatively, the
CS
pin can be taken high
to terminate the operation.
t
4
R W D5 D4 LSB
MSB MSB – 1 MSB – 2 LSB
t
3
t
9
t
2
t
5
t
6
t
7
t
8
t
11
t
10
t
1
t
12
CS
SCLK
1 2 3 4 32
DOUT
THREE-
STATE
THREE-
STATE
DIN
10660-041
Figure 35. Serial Interface Timing Diagram
POINTER [D5:D0]
DIN [D15:D8]
DIN [D7:D0]
CS
DIN
DOUT
R W
DOUT [D15:D0]
1
1
PROVIDED THE READ BIT IS SET.
10660-042
Figure 36. Accessing a 16-Bit Register