Datasheet

Data Sheet AD7292
Rev. 0 | Page 17 of 40
TEMPERATURE SENSOR
The AD7292 contains one local temperature sensor. The on-chip,
band gap temperature sensor measures the temperature of the
AD7292 die. The temperature sensor input gathers data and
computes a value over a period of several hundred microseconds.
The temperature measurement takes place continuously in the
background, leaving the user free to perform conversions on the
other channels.
After a temperature value is computed, a signal passes to the
control logic to initiate a conversion automatically. If an ADC
conversion is in progress, the temperature sensor conversion is
performed as soon as the ADC conversion is completed. If the
ADC is idle, the temperature sensor conversion takes place
immediately.
The T
SENSE
conversion result register stores the result of the last
conversion on the temperature channel; this result can be read at
any time provided that the temperature sensor is enabled via the
temperature sensor subregister within the configuration register
bank (see the Temperature Sensor Subregister (Address 0x20)
section).
Temperature readings from the ADC are stored in the T
SENSE
conversion result register. Results are in 14-bit straight binary
format and accommodate both positive and negative tempera-
ture measurements. Bit D0 and Bit D1 hold alert flags; Bit D2
stores the LSB, which corresponds to 0.03125°C if the digital
filter is enabled.
Table 12 provides examples of temperature sensor data. An output
of all 0s is equal to −256°C; this value is output by the AD7292
until the first measurement is completed. Note that when digital
filtering is disabled, Bit D3 and Bit D2 of the T
SENSE
conversion
result register are set to 0, producing a 12-bit straight binary result
with an LSB of 0.125°C. When the T
SENSE
conversion result is
read via the ADC data register (Address 0x01), the temperature
sensor result is a 10-bit result with an LSB that equates to 0.5°C.
Table 12. Temperature Sensor Data Format
Temperature (°C)
T
SENSE
Conversion Result Register,
Bits[D15:D2]
−40 01 1011 0000 0000
−25 01 1100 1110 0000
−10 01 1110 1100 0000
−0.03125 01 1111 1111 1111
0 10 0000 0000 0000
+0.03125 10 0000 0000 0001
[phone] 0000
[phone] 0000
[phone] 0000
[phone] 0000
[phone] 0000
[phone] 0000
DAC OPERATION
The four DACs of the AD7292 provide digital control with 10 bits
of resolution. DAC outputs VOUT0 to VOUT3 feature an output
voltage range up to 5 V (LSB of 4.88 mV).
The DAC output buffer can be controlled via software using the
GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 subregisters
within the configuration register bank, or via hardware using
the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins.
DIGITAL I/O PINS
To aid in system monitoring, the AD7292 features 12 digital I/O
pins. All 12 pins can be configured as GPIO pins. Six of the digital
I/O pins can be configured for other functionality; on power-up,
the non-GPIO functionality of these six pins is enabled by default.
For more information, see the Digital Output Driver Subregister
(Address 0x01) section and the Digital I/O Function Subregister
(Address 0x02) section.
GPIO0/ALERT0 and GPIO1/ALERT1 Pins
When Pin 27 and Pin 26 (GPIO0/ALERT0 and GPIO1/ALERT1,
respectively) are configured as alert pins, they act as out-of-range
indicators that become active when the selected conversion result
exceeds the high or low limit stored in the alert limits register bank.
The polarity of the alert output pins can be set to active high or
active low via the general subregister within the configuration
register bank (see the General Subregister (Address 0x08) section).
GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Pins
When Pin 25 and Pin 23 (GPIO2/DAC DISABLE0 and GPIO4/
DAC DISABLE1, respectively) are configured as DAC disable pins,
they can be used to power down the selected DAC outputs, as
determined by the contents of the GPIO2/DAC DISABLE0 and
GPIO4/DAC DISABLE1 subregisters within the configuration
register bank. For more information, see the GPIO2/DAC
DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address
0x30 and Address 0x31) section.
GPIO3/LDAC Pin
When Pin 24 (GPIO3/LDAC) is configured as an LDAC pin,
the DAC registers are updated when this input pin is taken high.
GPIO6/BUSY Pin
Pin 21 (GPIO6/BUSY) can be configured as a general-purpose
input/output or as a busy output pin. When configured as a busy
output pin, this pin transitions high when a conversion starts
and remains high until the conversion is completed.