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Table Of Contents

10-Bit Monitor and Control System with ADC,

DACs, Temperature Sensor, and GPIOs

Data Sheet

AD7292

Rev. 0 Document Feedback

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FEATURES

10-bit SAR ADC

8 multiplexed analog input channels

Single-ended mode of operation

Differential mode of operation

5 V analog input range

REF

, 2 × V

REF

, or 4 × V

REF

input ranges

Input measured with respect to A

GND

or V

4 monotonic, 10-bit, 5 V DACs

2 µs settling time

Power-on reset to 0 V

10 mA sink and source capability

Internal temperature sensor

±1°C accuracy

12 general-purpose digital I/O pins

Internal 1.25 V reference

Built-in monitoring features

Minimum and maximum value register for each channel

Programmable alert thresholds

Programmable hysteresis

SPI interface

Temperature range: −40°C to +125°C

Package type: 36-lead LFCSP

APPLICATIONS

Base station power amplifier (PA) monitoring and control

RF control loops

Optical communication system control

General-purpose system monitoring and control

FUNCTIONAL BLOCK DIAGRAM

CONTROL

LOGIC

BUF

AD7292

T/H

VIN1

VIN6

MUX

VIN7

VIN0

VOUT1

REF

OUT

BUF

TEMPERATURE

SENSOR

10-BIT

SAR ADC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

VOUT2

VOUT3

VOUT0

SPI

INTERFACE

GPIO0/ALERT0

GPIO1/ALERT1

GPIO2/DAC DISABLE0

GPIO5

GPIO4/DAC DISABLE1

GPIO3/LDAC

VIN2

VIN5

GPIO6/BUSY

GND

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GND

DIN

SCLK

DOUT

VIN4

VIN3

DRIVE

DIGITAL I/Os

ALERT AND LIMIT

REGISTERS

1.25V

REF

÷4

10660-001

Figure 1.

GENERAL DESCRIPTION

The AD7292 contains all the functionality required for general-

purpose monitoring of analog signals and control of external

devices, integrated into a single-chip solution. The AD7292

features an 8-channel, 10-bit SAR ADC, four 10-bit DACs, a

±1°C accurate internal temperature sensor, and 12 GPIOs to

aid system monitoring and control.

The 10-bit, high speed, low power successive approximation

ended input signals. Differential operation is also available by

configuring VIN0 and VIN1 to operate as a differential pair.

The AD7292 offers a register programmable ADC sequencer,

which enables the selection of a programmable sequence of

channels for conversion.

Four 10-bit digital-to-analog converters (DACs) provide outputs

from 0 V to 5 V. A n internal, high accuracy, 1.25 V reference

provides a separately buffered reference source for both the ADC

and the DACs.

A high accuracy band gap temperature sensor is monitored and

digitized by the 10-bit ADC to give a resolution of 0.03125°C.

The AD7292 also features built-in limit and alarm functions.

The AD7292 is a highly integrated solution offered in a 36-lead

LFCSP package with an operating temperature range of −40°C

to +125°C.

Summary of content (40 pages)

PAGE 1
0-Bit Monitor and Control System with ADC, DACs, Temperature Sensor, and GPIOs AD7292 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM ÷4 1.
PAGE 2
AD7292 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADC Sequence Register (Address 0x03) ................................. 21 Applications ....................................................................................... 1 Configuration Register Bank (Address 0x05) .......................... 21 Functional Block Diagram ..............................................................
PAGE 3
Data Sheet AD7292 SPECIFICATIONS ADC SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = −40°C to +125°C, unless otherwise noted. Specifications apply to single-ended mode only, unless otherwise noted. Table 1. Parameter DC ACCURACY Resolution Integral Nonlinearity (INL) 1 Min Typ Max ±0.11 ±0.5 ±0.6 ±0.99 ±8 ±12 ±1 10 ±0.5 ±4.17 Bits LSB LSB LSB mV mV mV ppm/°C % FS % FS % FS ppm/°C 61.5 61.5 dB dB −84 84.
PAGE 4
AD7292 Parameter EXTERNAL REFERENCE Reference Input Voltage Data Sheet Min 4.75 Input Resistance 1 Typ Max Unit Test Conditions/Comments AVDD V Internal reference used to calibrate temperature sensor 100 kΩ Specifications also apply to differential mode. DAC SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = −40°C to +125°C, unless otherwise noted. Table 2.
PAGE 5
Data Sheet AD7292 GENERAL SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = −40°C to +125°C, unless otherwise noted. Table 3. Parameter LOGIC INPUTS Input High Voltage, VIH Min Typ Unit Test Conditions/Comments 0.3 × VDRIVE 0.2 × VDRIVE ±1 V V V V μA pF V VDRIVE = 2.3 V to 5.25 V VDRIVE = 1.8 V to 1.95 V VDRIVE = 2.3 V to 5.25 V VDRIVE = 1.8 V to 1.95 V 0.7 × VDRIVE 0.
PAGE 6
AD7292 Data Sheet TIMING SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, CL = 27 pF, TA = −40°C to +125°C, unless otherwise noted. 1 Table 5.
PAGE 7
Data Sheet AD7292 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter AVDD to AGND DVDD to DGND VDRIVE to DGND VINx to AGND VOUTx to AGND Digital Inputs/Outputs to DGND CS, SCLK, DIN, DOUT to DGND REFOUT to AGND REFIN to AGND DGND to AGND Operating Temperature Range Storage Temperature Range Junction Temperature (TJ max) ESD, Human Body Model Reflow Soldering Peak Temperature Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +6 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.
PAGE 8
AD7292 Data Sheet 36 35 34 33 32 31 30 29 28 REFIN VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 AD7292 TOP VIEW (Not to Scale) 27 26 25 24 23 22 21 20 19 GPIO0/ALERT0 GPIO1/ALERT1 GPIO2/DAC DISABLE0 GPIO3/LDAC GPIO4/DAC DISABLE1 GPIO5 GPIO6/BUSY GPIO7 REFOUT NOTES 1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND AND CAN BE SOLDERED TO THE GROUND PLANE OF THE SYSTEM.
PAGE 9
Data Sheet Pin No. 26 Mnemonic GPIO1/ALERT1 27 GPIO0/ALERT0 28 to 35 VIN0 to VIN7 36 REFIN EPAD EPAD AD7292 Description General-Purpose Input/Output Pin (GPIO1). Alert Pin 1 (ALERT1). When configured as an alert, this pin acts as an out-of-range indicator and becomes active when the conversion result violates the high or low limit stored in the alert limits register bank. The polarity of the alert signal is controlled using the general subregister within the configuration register bank.
PAGE 10
AD7292 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AVDD = 5V DVDD = 5V VDRIVE = 3V TA = 25°C fSAMPLE = 200kSPS RANGE = 0V TO VREF SINGLE-ENDED MODE SNR = 61.6dB THD = –84.0dB SINAD = 61.49dB SFDR = 79.05dB –40 –60 –80 –60 –80 –100 10 20 30 40 50 60 70 80 90 100 –120 10660-004 0 INPUT FREQUENCY (kHz) 0.3 30 40 50 60 70 80 90 100 TA = 25°C AVDD = 4.75V DVDD = 5.25V WCP INL = 0.091LSB VDRIVE = 3.3V WCN INL = –0.
PAGE 11
Data Sheet AD7292 0.4 AVDD = 5V DVDD = 3V VDRIVE = 3V fSAMPLE = 225kSPS INTERNAL REFERENCE SINGLE-ENDED MODE 0.4 0.2 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –40 0V TO 0V TO 0V TO 0V TO 0V TO 0V TO (AVDD (AVDD –20 VREF , –INL VREF , +INL 2 × VREF , –INL 2 × VREF , +INL 4 × VREF , –INL 4 × VREF , +INL – 4 × VREF ) TO AVDD, –INL – 4 × VREF ) TO AVDD, +INL 0 0 –0.1 –0.3 20 40 60 TEMPERATURE (°C) 80 100 120 AVDD = 5V DVDD = 3V VDRIVE = 3V fSAMPLE = 225kSPS INTERNAL REFERENCE SINGLE-ENDED MODE 0.1 –0.
PAGE 12
AD7292 Data Sheet 1.3 900 AVDD = 5V DVDD = 5V VDRIVE = 2.5V TA = 25°C OCCURRENCES 700 1.2 REFERENCE VOLTAGE (V) 800 600 500 400 300 1.1 1.0 AVDD = 5V DVDD = VDRIVE = 3V fSAMPLE = 225kSPS ANALOG INPUT RANGE = AVDD – 4 × VREF TA = 25°C 0.9 0.8 200 512 0.6 OUTPUT CODE 1k 0.15 DNL ERROR (LSB) 0.3 0.1 –0.1 AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V TA = 25°C INTERNAL REFERENCE –0.5 256 384 512 640 768 896 0.05 –0.05 AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V TA = 25°C INTERNAL REFERENCE –0.
PAGE 13
Data Sheet AD7292 0.4 5.0 4.5 DVDD = 5V VDRIVE = 3.3V INTERNAL REFERENCE 0.3 4.0 GAIN ERROR (%FSR) OFFSET ERROR (mV) 0.2 3.5 3.0 2.5 AVDD = 5.25V 2.0 1.5 AVDD = 4.75V 0.1 0 –0.1 AVDD = 5.25V –0.2 1.0 DVDD = 5V VDRIVE = 3.3V INTERNAL REFERENCE –20 0 20 40 60 80 100 120 –0.4 –40 TEMPERATURE (°C) –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 22. DAC Offset Error vs. Temperature Figure 25. DAC Gain Error vs. Temperature 0.10 4.996 AVDD = 5.25V DVDD = 5V VDRIVE = 3.
PAGE 14
AD7292 Data Sheet 6.0 1.6 AVDD = DVDD = VDRIVE = 5V 10 DEVICES 1.4 5.8 5.6 ERROR (°C) 1.0 0.8 0.6 0.4 0.2 5.2 5.0 4.8 4.6 4.4 –0.2 4.2 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 10660-031 0 –0.4 –40 Figure 28. Temperature Sensor Error vs.
PAGE 15
Data Sheet AD7292 THEORY OF OPERATION ANALOG INPUTS VIN+ VREF p-p The analog input range is programmed to one of these values: 0 V to VREF, 0 V to 2 × VREF, or 0 V to 4 × VREF. For information about programming the input range, see the VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) section. In 0 V to 2 × VREF mode, the input is scaled by a factor of 2 before the conversion takes place.
PAGE 16
AD7292 Data Sheet ADC TRANSFER FUNCTIONS The LSB size depends on the input range selected (see Table 9). The output coding of the AD7292 is 10-bit straight binary for the analog input channels. The designated code transitions occur at successive LSB values. Table 9. Input Range and LSB Size To select the input range, set the appropriate bits in the VIN RANGE1 and VIN RANGE0 subregisters of the configuration register bank (see Table 10).
PAGE 17
Data Sheet AD7292 TEMPERATURE SENSOR DAC OPERATION The AD7292 contains one local temperature sensor. The on-chip, band gap temperature sensor measures the temperature of the AD7292 die. The temperature sensor input gathers data and computes a value over a period of several hundred microseconds. The temperature measurement takes place continuously in the background, leaving the user free to perform conversions on the other channels.
PAGE 18
AD7292 Data Sheet SERIAL PORT INTERFACE (SPI) The AD7292 serial port interface (SPI) allows the user to configure the device for specific functions and operations through an internal structured register space. The interface consists of four signals: CS, SCLK, DIN, and DOUT. The SPI reference level is set by Pin 5 (VDRIVE) to a level in the range of 1.8 V to 5.25 V. Table 13.
PAGE 19
Data Sheet AD7292 CS R W DIN POINTER [D5:D0] SUBPOINTER [D7:D0] DIN [D7:D0] 1PROVIDED 10660-043 DOUT [D7:D0] 1 DOUT THE READ BIT IS SET. Figure 37. Accessing an 8-Bit Subregister Within a Register Bank CS R W POINTER [D5:D0] SUBPOINTER [D7:D0] DIN [D15:D8] DIN [D7:D0] DOUT [D15:D0] 1 DOUT 1PROVIDED THE READ BIT IS SET. Figure 38. Accessing a 16-Bit Subregister Within a Register Bank Rev.
PAGE 20
AD7292 Data Sheet REGISTER STRUCTURE The AD7292 contains internal registers that store conversion results, high and low conversion limits, and information to configure and control the device (see Figure 39). Each register has an address; the address pointer register points to the address when communicating with the register. Some registers and subregisters contain reserved bits. The AD7292 allows either a 0 or a 1 to be written to these reserved bits.
PAGE 21
Data Sheet AD7292 REGISTER DESCRIPTIONS VENDOR ID REGISTER (ADDRESS 0x00) CONFIGURATION REGISTER BANK (ADDRESS 0x05) The 16-bit, read-only vendor ID register stores the Analog Devices vendor ID, 0x0018. The vendor ID register is provided to identify the AD7292 to an SPI master such as a microcontroller. The configuration register bank subregisters are listed in Table 15. On power-up, the subregisters within the configuration register bank contain all 0s by default.
PAGE 22
AD7292 Data Sheet Digital Output Driver Subregister (Address 0x01) Digital I/O Function Subregister (Address 0x02) The 16-bit digital output driver subregister enables the output drivers of the digital I/O pins. Setting Bits[D11:D0] to 1 enables the corresponding digital I/O output driver. Six of the 12 digital I/O pins offer mixed functionality (see Table 18).
PAGE 23
Data Sheet AD7292 General Subregister (Address 0x08) When the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins are configured as DAC disable pins (via the digital I/O function subregister), Bits[D2:D1] of the 16-bit general subregister control the power disable mode of these two pins. Table 19 shows the four power disable modes.
PAGE 24
AD7292 Data Sheet VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) The 16-bit VIN RANGE0 and VIN RANGE1 subregisters specify a divide-by-2 factor for each analog input channel, VIN0 to VIN7. A divide-by-2 factor from both the VIN RANGE0 and VIN RANGE1 subregisters can be applied to each channel; that is, setting Bit D0 of VIN RANGE1 and Bit D0 of VIN RANGE0 enables a divide-by-4 factor for the VIN0 input range.
PAGE 25
Data Sheet AD7292 ADC Sampling Mode Subregister (Address 0x12) Table 22 lists the bit function descriptions for the 16-bit ADC sampling mode subregister. Bit D0 allows the user to enable differential input mode for analog input channels VIN0 and VIN1. When enabled and converting on VIN0, the differential input to the ADC is (VIN0, VIN1). When enabled and converting on VIN1, the differential input to the ADC is (VIN1, VIN0). To use differential mode, Bit D0 must be set to 1.
PAGE 26
AD7292 Data Sheet VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x13 and Address 0x14) The 16-bit VIN ALERT0 and VIN ALERT1 subregisters enable the routing of alerts from the analog input channels, VIN0 to VIN7, to the GPIO0/ALERT0 and GPIO1/ALERT1 pins (see Table 23 and Table 24).
PAGE 27
Data Sheet AD7292 VIN Filter Subregister (Address 0x15) The 16-bit VIN filter subregister enables digital filtering of the analog inputs channels. The digital filter consists of a simple low-pass filter function to help reduce unwanted noise on dc signals. Writing a 1 to Bits[D7:D0] in this subregister enables digital filtering of the corresponding analog input channel (see Table 25). On power-up, the VIN filter subregister contains all 0s by default.
PAGE 28
AD7292 Data Sheet Temperature Sensor Subregister (Address 0x20) The 16-bit temperature sensor subregister enables temperature sensor conversions and digital filtering of the temperature sensor channel. To enable temperature sensor conversions or digital filtering, the corresponding bit in the temperature sensor subregister must be set to 1 (see Table 27). On power-up, the temperature sensor subregister contains all 0s by default.
PAGE 29
Data Sheet AD7292 GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31) The 16-bit, read/write GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 subregisters specify which DAC channels are disabled by the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins. For example, when Bit D0 in the GPIO2/DAC DISABLE0 subregister is set to 1, the GPIO2/DAC DISABLE0 pin disables DAC output VOUT0 when the pin is taken high. On power-up, these subregisters contain all 0s by default.
PAGE 30
AD7292 Data Sheet ALERT LIMITS REGISTER BANK (ADDRESS 0x06) Table 31. Alert Limits Register Bank Subregisters The alert limits register bank comprises subregisters that set the high and low alert limits for the eight analog input channels and the temperature sensor channel (see Table 31). Each subregister is 16 bits in length; values are 10-bit, left-justified (padded with 0s as the 6 LSBs).
PAGE 31
Data Sheet AD7292 ALERT FLAGS REGISTER BANK (ADDRESS 0x07) If a conversion result activates an alert (as specified in the alert limits register bank), the alert flags register bank can be read to obtain more information about the alert. This register bank contains the ADC alert flags and TSENSE alert flags subregisters. Both subregisters store flags that are triggered when the minimum or maximum conversion limits, as defined in the alert limits register bank, are exceeded. Table 32.
PAGE 32
AD7292 Data Sheet MINIMUM AND MAXIMUM REGISTER BANK (ADDRESS 0x08) OFFSET REGISTER BANK (ADDRESS 0x09) The minimum and maximum register bank contains the minimum and maximum conversion values for each of the eight analog input channels and the temperature sensor channel. Values are 10-bit, left justified. The minimum and maximum subregisters are cleared when a value is written to them—that is, they return to their power-up values.
PAGE 33
Data Sheet AD7292 DAC BUFFER ENABLE REGISTER (ADDRESS 0x0A) GPIO REGISTER (ADDRESS 0x0B) The 16-bit, read/write DAC buffer enable register enables the DAC output buffers. Setting the appropriate bit to 1 enables the corresponding DAC output buffer (see Table 41). On power-up, the DAC buffer enable register contains all 0s by default.
PAGE 34
AD7292 Data Sheet CONVERSION COMMAND REGISTER (ADDRESS 0x0E) TSENSE CONVERSION RESULT REGISTER (ADDRESS 0x20) The conversion command signals the ADC to begin conversions. See the ADC Conversion Control section for more information. The 16-bit, read-only TSENSE conversion result register stores the ADC data generated from the internal temperature sensor. The temperature data is stored in a 14-bit straight binary format. Bit D2 has a weight of 0.03125°C.
PAGE 35
Data Sheet AD7292 ADC CONVERSION CONTROL ADC CONVERSION COMMAND In this example, the ADC sequence register is programmed to convert on analog input channels VIN0 and VIN1. The AD7292 stays in conversion mode and performs a new ADC conversion at the end of each read until the CS input signal is taken high. To initiate an ADC conversion on a channel, the conversion command must be written to the AD7292.
PAGE 36
AD7292 Data Sheet CS 1 8 16 1 8 16 24 32 1 8 16 24 SCLK POINT TO ADC DATA REGISTER POINT TO ADC DATA REGISTER ISSUE CONVERSION COMMAND POINT TO ADC DATA REGISTER ISSUE CONVERSION COMMAND VIN0 RESULT [D15:D0] DOUT BUSY VIN1 RESULT [D15:D0] CONVERT VIN0 10660-048 DIN CONVERT VIN1 Figure 42.
PAGE 37
Data Sheet AD7292 DAC OUTPUT CONTROL To set the DAC output voltage codes, the user must write to the DAC channel registers (Address 0x30 to Address 0x33). Figure 44 shows an example of how to set the DAC output voltage codes. 1. 2. 3. 4. When the LDAC bit in the DAC channel register is set to 1, the 10-bit DAC value is stored, but the DAC channel output is not updated.
PAGE 38
AD7292 Data Sheet ALERTS AND LIMITS ALERT LIMIT MONITORING FEATURES The alert limits register bank comprises subregisters that set the high and low alert limits for the eight analog input channels and the temperature sensor channel (see Table 31). Each subregister is 16 bits in length; values are 10-bit, left-justified (padded with 0s as the 6 LSBs). On power-up, the low limit and hysteresis subregisters contain all 0s, whereas the high limit subregisters are set to 0xFFC0.
PAGE 39
Data Sheet AD7292 ALERT FLAGS REGISTER BANK The alert flags register bank contains two subregisters: the ADC alert flags subregister and the TSENSE alert flags subregister. The ADC alert flags subregister stores alerts for the analog voltage conversion channels, VIN0 to VIN7. The TSENSE alert flags subregister stores alerts for the temperature sensor channel.
PAGE 40
AD7292 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 36 28 27 1 0.50 BSC 4.05 3.90 SQ 3.85 EXPOSED PAD 19 TOP VIEW 0.80 0.75 0.70 0.70 0.60 0.40 SEATING PLANE 9 18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PIN 1 INDICATOR 10 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 03-29-2012-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 47.