Datasheet

Data Sheet AD7291
Rev. B | Page 25 of 28
The example in Figure 28 shows the command mode convert-
ing on a sequence of channels including V
IN0
, V
IN1
, and V
IN2
.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device (AD7291) asserts an
acknowledge on SDA.
4. The master sends the command register address (0x00).
5. The slave asserts an acknowledge on SDA.
6. The master sends the first data byte (0xE0) to the command
register, which selects the V
IN0
, V
IN1
, and V
IN2
channels.
7. The slave asserts an acknowledge on SDA.
8. The master sends the second data byte (0x20) to the com-
mand register.
9. The slave asserts an acknowledge on SDA.
10. The master sends the result register address (0x01).
11. The slave asserts an acknowledge on SDA.
12. The master sends the 7-bit slave address followed by the
write bit (high).
13. The slave (AD7291) asserts an acknowledge on SDA.
14. The master receives a data byte, which contains the
channel address bits and the four MSBs of the converted
result for Channel V
IN0
.
15. The master then asserts an acknowledge on SDA.
16. The master receives the second data byte, which contains
the eight LSBs of the converted result for Channel V
IN0
. The
master then asserts on acknowledge on SDA.
17. Step 11 and Step 12 repeat for Channel V
IN1
and
Channel V
IN2
.
18. Once the master has received the results from all the
selected channels, the slave again converts and outputs
the result for the first channel in the selected sequence.
Step 12 to Step 14 are repeated.
19. The master asserts a not acknowledge on SDA and a stop
condition on SDA to end the conversion and exit
command mode.
To change the conversion sequence, rewrite a new sequence to
the command mode. If a new write to the command register is
performed while an existing conversion sequence is underway,
the existing conversion sequence is terminated and the next
conversion performed is the first selected channel from the new
sequence. The maximum throughput that can be achieved using
this mode with a 400 kHz I
2
C clock is (400 kHz/18) = 22.2 kSPS.
08711-016
S SA
P
...
...
0 SA SA SACOMMAND = 0xE0 COMMAND = 0x20
A
V
IN0
[11:8]
A
POINT TO RESULT REG (0x01) SR 1 SASA CH AD (0000)
...
A
V
IN2
[11:8]
*
*
*
*
A A
...
...
AV
IN0
[7:0]
...
........
A
* = POSITION OF SAMPLING START
SLAVE ADDRESS
POINT TO COMMAND REG (0x00)
V
IN0
[7:0]
ACH AD (0001) A
...
V
IN1
[7:0]V
IN1
[11:8]
V
IN0
[11:8]
SLAVE ADDRESS
V
IN2
[7:0]
V
IN2
[7:0]
CH AD (0010) CH ID (0000)
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
SA = SLAVE ACKNOWLEDGE
A = NOT ACKNOWLEDGE
Figure 28. Command Mode Operation