Datasheet

Data Sheet AD7291
Rev. C | Page 21 of 28
I
2
C INTERFACE
Control of the AD7291 is carried out via the I
2
C compatible
serial bus. The AD7291 is connected to this bus as a slave device
under the control of a master device such as the processor.
SERIAL BUS ADDRESS BYTE
The first byte the user writes to the device is the slave address
byte. Similar to all I
2
C-compatible devices, the AD7291 has a
7-bit serial address. The three MSBs of this address are set to
010. The four LSBs are user-programmable by the three-state
input pins, AS0 and AS1, as shown in Table 31.
In Table 31, H means tie the pin to V
DRIVE
, L means tie the pin
to GND, and NC refers to a pin left floating. Note that in this
final case, the stray capacitance on the pin must be less than
30 pF to allow correct detection of the floating state; therefore,
any PCB trace must be kept as short as possible.
Table 31. Slave Address Control Using Three-State Input Pins
AS1 AS0
Slave Address (A6 to A0)
Binary Hex
H H 010 0000 0x20
H NC 010 0010 0x22
H L 010 0011 0x23
NC H 010 1000 0x28
NC NC 010 1010 0x2A
NC L 010 1011 0x2B
L H 010 1100 0x2C
L NC 010 1110 0x2E
L L 010 1111 0x2F
GENERAL I2C TIMING
Figure 24 shows the timing diagram for general read and write
operations using an I
2
C-compliant interface.
When no device is driving the bus, both SCL and SDA are high.
This is known as the idle state. When the bus is idle, the master
initiates a data transfer by establishing a start condition, defined
as a high-to-low transition on the serial data line (SDA) while
the serial clock line (SCL) remains high. This indicates that a
data stream follows. The master device is responsible for
generating the clock.
Data is sent over the serial bus in groups of nine bits—eight bits
of data from the transmitter followed by an acknowledge bit (ACK)
from the receiver. Data transitions on the SDA line must occur
during the low period of the clock signal and remain stable during
the high period. The receiver must pull the SDA line low during
the acknowledge bit to signal that the preceding byte is received
correctly. If this is not the case, cancel the transaction.
The first byte that the master sends must consist of a 7-bit slave
address, followed by a data direction bit. Each device on the
bus has a unique slave address; therefore, the first byte sets up
communication with a single slave device for the duration of the
transaction.
The transaction can be used either to write to a slave device
(data direction bit = 0) or to read data from it (data direction
bit = 1). In the case of a read transaction, it is often necessary
first to write to the slave device (in a separate write transaction)
to tell it from which register to read. Reading and writing
cannot be combined in one transaction.
When the transaction is complete, the master can keep control
of the bus, initiating a new transaction by generating another
start bit (high-to-low transition on SDA while SCL is high).
This is known as a repeated start (SR). Alternatively, the bus
can be relinquished by releasing the SCL line followed by the
SDA line. This low-to-high transition on SDA while SCL is high
is known as a stop bit (P), and it leaves the I
2
C bus in the idle
state (no current is consumed by the bus).
The example in Figure 24 shows a simple write transaction
with an AD7291 as the slave device. In this example, the
AD7291 register pointer is being set up for a future read
transaction.
P7 P6 P5 P4 P3 P2 P1 P0
START COND
BY MASTER
ACK. BY
AD7291
SLAVE ADDRESS BYTE
ACK. BY
AD7291
SCL
SD
A
REGISTER ADDRESS
STOP BY
MASTER
USER PROGRAMMABLE 5 LSBs
R/W
A6 A5 A4 A3 A2 A1 A0
0
8711-040
Figure 24. General I
2
C Timing