Datasheet

AD7280A
Rev. 0 | Page 20 of 48
Note that 90 s should be allowed before initiating any conver-
sions following any change to Bits[D15:D14]. This time should
be allowed between writing to the control register to change the
selected conversions and initiating the first conversion.
Conversions that are initiated by the rising edge of the
CS
pin
require two separate write commands to the control register. The
first command configures the AD7280A for the required
acquisition time; the second command, following a delay of
90 s, initiates the conversion on the rising edge of
CS
.
After the completion of all requested conversions, the results
can be read back from either a single device or from all devices
in a daisy chain by using the SPI and daisy-chain interfaces. For
more information, see the Serial Interface section and the
Daisy-Chain Interface section.
As shown in Figure 32, a wait time, t
WA I T
, is required between the
completion of conversions and the start of readback. This time
is required to synchronize the high speed conversion clock and
the lower speed clock used for all other AD7280A operations.
The minimum value of t
WA I T
is 5 s.
Acquisition Time
The time required to acquire an input signal depends on how
quickly the sampling capacitor is charged. This, in turn, depends
on the input impedance and any external components placed on
the analog inputs. The default acquisition time of the AD7280A
on initial power-up is 400 ns. This time can be increased in steps
of 400 ns up to 1.6 µs to provide flexibility in selecting external
components on the analog inputs. The acquisition time is selected
by writing to Bits[D6:D5] in the control register (see Table 9).
Table 9. Analog Input Acquisition Time
Bits[D6:D5] Acquisition Time
00 400 ns
01 800 ns
10 1.2 µs
11 1.6 µs
The acquisition time required is calculated using the following
formula:
t
ACQ
= 10 × ((R
SOURCE
+ R) × C)
where:
R
SOURCE
should include any extra source impedance on the
analog input between the external capacitors (100 nF) and the
input pins. It does not include any extra source impedance, for
example, the 10 kΩ series resistors, which are between the
battery cells and the external capacitors.
R is the resistance seen by the track-and-hold amplifier looking
at the input, 300 Ω.
C is the sampling capacitance, that is, the value of the sampling
capacitor, 15 pF.
Conversion Averaging
The AD7280A includes an option where the acquisition and
conversion of each cell input can be repeated with an averaged
conversion result being stored in the individual register. The
averaged conversion result can then be read back through the
SPI interface in the same manner as a standard conversion result.
The AD7280A can be programmed, through Bits[D10:D9] of the
control register, to complete one, two, four, or eight conversions.
The default on power-up is a single conversion per channel, that
is, no averaging.
Selection of the two, four, or eight average options through the
control register causes the control sequence of both the high
voltage and low voltage input multiplexers to be reconfigured to
allow the additional acquisitions and conversions to be completed.
In each case, the requested number of conversions is completed
on each channel before beginning the acquisition and conversion
of the next channel in sequence. For example, if an average of two
conversions is requested, the new sequence is Voltage Channel 6,
Voltage Channel 6, Voltage Channel 5, Voltage Channel 5, Voltage
Channel 4, and so on.
It should also be noted that when the high voltage multiplexer
is reconfigured, 90 s should be allowed before initiating any
conversions. This time should be allowed between writing to
the control register to select averaging and initiating the first
conversion. Conversions that are being initiated by the rising
edge of the
CS
pin require two separate write commands to the
control register. The first command configures the AD7280A
for the required averaging, and the second command, after a
delay of 90 s, initiates the conversion on the rising edge of
CS
.
Suggested External Component Configuration on
Analog Inputs
As described in the Acquisition Time section, the acquisition
time of the AD7280A is selected by the status of Bits[D6:D5] in
the control register. This provides flexibility in selecting external
components on the analog inputs. A suggested configuration
for placing external components on the analog inputs to the
AD7280A is shown in Figure 33.
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
AD7280A
10kΩ
10kΩ
100nF
10kΩ
10kΩ
100nF
100nF
10kΩ
10kΩ
100nF
10kΩ
100nF
100nF
09435-016
Figure 33. External Series Resistance and Shunt Capacitance