Datasheet

AD7276/AD7277/AD7278
Rev. C | Page 8 of 28
Parameter A Grade
1, 2
B Grade
1, 2
Unit Test Conditions/Comments
POWER REQUIREMENTS
V
DD
2.35/3.6 2.35/3.6 V min/max
I
DD
Digital I/Ps = 0 V or V
DD
Normal Mode (Static) 0.5 0.5 mA typ V
DD
= 3.6 V, SCLK on or off
Normal Mode (Operational) 5.5 5.5 mA max V
DD
= 2.35 V to 3.6 V, f
SAMPLE
= 3 MSPS
3.5 3.5 mA typ V
DD
= 3 V
Partial Power-Down Mode (Static) 34 34 μA typ
Full Power-Down Mode (Static) 2 2 μA max −40°C to +85°C, typically 0.1 μA
10 10 μA max +85°C to +125°C
Power Dissipation
5
Normal Mode (Operational) 19.8 19.8 mW max V
DD
= 3.6 V, f
SAMPLE
= 3 MSPS
10.5 10.5 mW typ V
DD
= 3 V
Partial Power-Down 102 102 μW typ V
DD
= 3 V
Full Power-Down 7.2 7.2 μW max V
DD
= 3.6 V, −40°C to +85°C
1
Temperature range from −40°C to +125°C.
2
Typical specifications are tested with V
DD
= 3 V and at 25°C.
3
See the Terminology section.
4
Guaranteed by characterization.
5
See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS—AD7276/AD7277/AD7278
V
DD
= 2.35 V to 3.6 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 5.
Parameter
2
Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
3
500 kHz min
4
48 MHz max B grade
16 MHz max Y grade
t
CONVERT
14 × t
SCLK
AD7276
12 × t
SCLK
AD7277
10 × t
SCLK
AD7278
t
QUIET
4 ns min
Minimum quiet time required between the bus relinquish and the
start of the next conversion
t
1
3 ns min
Minimum CS
pulse width
t
2
6 ns min
CS
to SCLK setup time
t
3
5
4 ns max
Delay from CS
until SDATA three-state disabled
t
4
5
15 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min SCLK low pulse width
t
6
0.4 t
SCLK
ns min SCLK high pulse width
t
7
5
5 ns min SCLK to data valid hold time
t
8
14 ns max SCLK falling edge to SDATA three-state
5 ns min SCLK falling edge to SDATA three-state
t
9
4.2 ns max
CS
rising edge to SDATA three-state
T
POWER-UP
6
1 μs max Power-up time from full power-down
1
Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
2
Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
3
Mark/space ratio for the SCLK input is 40/60 to 60/40.
4
Minimum f
SCLK
at which specifications are guaranteed.
5
The time required for the output to cross the V
IH
or V
IL
voltage.
6
See the Power-Up Times section.