Datasheet

AD7276/AD7277/AD7278
Rev. C | Page 26 of 28
OUTLINE DIMENSIONS
102808-A
*
COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
13
45
2
6
2.90 BS
C
1.60 BSC
2.80 BSC
1.90
BSC
0.95 BSC
0.10 MAX
*
1.00 MAX
PIN 1
INDI
C
ATOR
*
0.90
0.87
0.84
0.60
0.45
0.30
0.50
0.30
0.20
0.08
SEATING
PLANE
8°
4°
0°
Figure 37. 6-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-6)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 38. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters