Datasheet

AD7276/AD7277/AD7278
Rev. C | Page 10 of 28
TIMING EXAMPLES
For the AD7276, if
CS
is brought high during the 14
th
SCLK rising
edge after the two leading zeros and 12 bits of the conversion
have been provided, the part can achieve the fastest throughput
rate, 3 MSPS. If
CS
is brought high during the 16
th
SCLK rising
edge after the two leading zeros and 12 bits of the conversion
and two trailing zeros have been provided, a throughput rate of
2.97 MSPS is achievable. This is illustrated in the following two
timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, f
SCLK
= 48 MHz and the
throughput is 3 MSPS. This produces a cycle time of t
2
+
12.5(1/f
SCLK
) + t
ACQ
= 333 ns, where t
2
= 6 ns minimum and
t
ACQ
= 67 ns.
This satisfies the requirement of 60 ns for t
ACQ
. Figure 6 also
shows that t
ACQ
comprises 0.5(1/f
SCLK
) + t
8
+ t
QUIET
, where
t
8
= 14 ns max. This allows a value of 43 ns for t
QUIET
, satisfying
the minimum requirement of 4 ns.
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, f
SCLK
= 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time of
t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 336 ns, where t
2
= 6 ns minimum and
t
ACQ
= 70 ns. Figure 7 shows that t
ACQ
comprises 2.5(1/f
SCLK
) + t
8
+
t
QUIET
, where t
8
= 14 ns max. This satisfies the minimum
requirement of 4 ns for t
QUIET.
04903-005
1 2 345 13141516
SCLK
S
DATA
THREE-STATETHREE-
STATE
2 LEADING
ZEROS
2 TRAILING
ZEROS
B
CS
t
3
t
CONVERT
t
2
ZEROZ DB11 DB10 DB9 DB1 DB0 ZERO ZERO
t
6
t
5
t
8
t
1
t
QUIET
1/THROUGHPUT
t
4
t
7
Figure 5. AD7276 Serial Interface Timing Diagram
04903-034
t
QUIET
t
CONVERT
1/THROUGHPUT
CS
1513
t
4
234
t
5
t
3
t
2
t
6
t
7
t
9
14
B
t
1
SCLK
SDATA
THREE-STATE
THREE-
STATE
2 LEADING
ZEROS
ZZERO
DB11 DB10 DB9 DB1 DB0
Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle
04903-006
12345 1312 14 15 16
SCL
K
B
CS
t
CONVERT
t
2
t
8
t
1
t
QUIET
1/THROUGHPUT
12.5(1/f
SCLK
) t
ACQUISITION
Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle