Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply MSOP 8

3 MSPS, 12-/10-/8-Bit

ADCs in 6-Lead TSOT

AD7276/AD7277/AD7278

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Throughput rate: 3 MSPS

Specified for V

of 2.35 V to 3.6 V

Power consumption

12.6 mW at 3 MSPS with 3 V supplies

Wide input bandwidth

70 dB SNR at 1 MHz input frequency

Flexible power/serial clock speed management

No pipeline delays

High speed serial interface

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

Temperature range: −40°C to +125°C

Power-down mode: 0.1 μA typical

6-lead TSOT package

8-lead MSOP package

AD7476 and AD7476A pin-compatible

GENERAL DESCRIPTION

The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed,

low power, successive approximation analog-to-digital converters

(ADCs), respectively. The parts operate from a single 2.35 V

to 3.6 V power supply and feature throughput rates of up to

3 MSPS. The parts contain a low noise, wide bandwidth track-

and-hold amplifier that can handle input frequencies in excess

of 55 MHz.

The conversion process and data acquisition are controlled

using

and the serial clock, allowing the devices to interface

with microprocessors or DSPs. The input signal is sampled on

the falling edge of

, and the conversion is also initiated at this

point. There are no pipeline delays associated with the part.

The AD7276/AD7277/AD7278 use advanced design techniques

to achieve very low power dissipation at high throughput rates.

The reference for the part is taken internally from VDD. This

allows the widest dynamic input range to the ADC; therefore,

the analog input range for the part is 0 to VDD. The conversion

rate is determined by the SCLK.

FUNCTIONAL BLOCK DIAGRAM

04903-001

T/H

CONTROL

LOGIC

12-/10-/8-BIT

SUCCESSIVE

APPROXIMATION

ADC

GND

AD7276/

AD7277/

AD7278

SCLK

SDATA

Figure 1.

Table 1.

Part Number Resolution Package

AD7276 12 8-Lead MSOP 6-Lead TSOT

AD7277 10 8-Lead MSOP 6-Lead TSOT

AD7278 8 8-Lead MSOP 6-Lead TSOT

AD7274

12 8-Lead MSOP 8-Lead TSOT

AD7273

10 8-Lead MSOP 8-Lead TSOT

Part contains external reference pin.

PRODUCT HIGHLIGHTS

1. 3 MSPS ADCs in a 6-lead TSOT package.

2. AD7476/AD7477/AD7478 and AD7476A/AD7477A/

AD7478A pin-compatible.

3. High throughput with low power consumption.

4. Flexible power/serial clock speed management. This allows

maximum power efficiency at low throughput rates.

5. Reference derived from the power supply.

6. No pipeline delay. The parts feature a standard successive

approximation ADC with accurate control of the sampling

instant via a

input and once-off conversion control.

Summary of content (29 pages)

PAGE 1
3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT AD7276/AD7277/AD7278 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD Throughput rate: 3 MSPS Specified for VDD of 2.35 V to 3.6 V Power consumption 12.6 mW at 3 MSPS with 3 V supplies Wide input bandwidth 70 dB SNR at 1 MHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Temperature range: −40°C to +125°C Power-down mode: 0.
PAGE 2
Powered by TCPDF (www.tcpdf.org) IMPORTANT LINKS for the AD7276_7277_7278* Last content update 11/12/2013 06:16 pm DOCUMENTATION SIMILAR PRODUCTS & PARAMETRIC SELECTION TABLES MS-2210: Designing Power Supplies for High Speed ADC 8- to 18-Bit SAR ADCs ...
PAGE 3
AD7276/AD7277/AD7278 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 General Description ......................................................................... 1 Circuit Information.................................................................... 16 Functional Block Diagram .........................................................
PAGE 4
AD7276/AD7277/AD7278 SPECIFICATIONS AD7276 SPECIFICATIONS VDD = 2.35 V to 3.6 V, B Grade and A Grade: fSCLK = 48 MHz, fSAMPLE = 3 MSPS, Y Grade: 1 fSCLK = 16 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 5
AD7276/AD7277/AD7278 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time4 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) Power Dissipation 6 Normal Mode (Operational) Partial Power-Down Full Power-Down A Grade 2, 3 B, Y Grade2,3 Unit Test Conditions/Comments 291 875 60 3 291 875 60 3 ns max ns max ns min MSPS max 14 SCLK cycles with SCLK at 48 MHz, B Grade 14 SCLK cycles
PAGE 6
AD7276/AD7277/AD7278 AD7277 SPECIFICATIONS VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted. Table 3.
PAGE 7
AD7276/AD7277/AD7278 Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) Power Dissipation 5 Normal Mode (Operational) Partial Power-Down Full Power-Down A Grade 1, 2 B Grade1, 2 Unit 2.35/3.6 2.35/3.6 V min/max 0.6 5.5 3.5 34 2 10 0.6 5.5 3.5 34 2 10 mA typ mA max mA typ μA typ μA max μA max −40°C to +85°C, typically 0.1 μA 85°C to 125°C 19.8 10.5 102 7.2 19.8 10.5 102 7.
PAGE 8
AD7276/AD7277/AD7278 AD7278 SPECIFICATIONS VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted. Table 4.
PAGE 9
AD7276/AD7277/AD7278 Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) Power Dissipation 5 Normal Mode (Operational) Partial Power-Down Full Power-Down A Grade 1, 2 B Grade1, 2 Unit 2.35/3.6 2.35/3.6 V min/max 0.5 5.5 3.5 34 2 10 0.5 5.5 3.5 34 2 10 mA typ mA max mA typ μA typ μA max μA max −40°C to +85°C, typically 0.1 μA +85°C to +125°C 19.8 10.5 102 7.2 19.8 10.5 102 7.
PAGE 10
AD7276/AD7277/AD7278 t4 t8 SCLK VIL Figure 2. Access Time After SCLK Falling Edge Figure 4. SCLK Falling Edge SDATA Three-State t7 SCLK 04903-003 VIH SDATA VIL 1.4V SDATA Figure 3. Hold Time After SCLK Falling Edge Rev.
PAGE 11
AD7276/AD7277/AD7278 This satisfies the requirement of 60 ns for tACQ. Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where t8 = 14 ns max. This allows a value of 43 ns for tQUIET, satisfying the minimum requirement of 4 ns. TIMING EXAMPLES For the AD7276, if CS is brought high during the 14th SCLK rising edge after the two leading zeros and 12 bits of the conversion have been provided, the part can achieve the fastest throughput rate, 3 MSPS.
PAGE 12
AD7276/AD7277/AD7278 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6.
PAGE 13
AD7276/AD7277/AD7278 GND 2 AD7276/ AD7277/ AD7278 6 VDD 1 CS SDATA 2 5 SDATA TOP VIEW VIN 3 (Not to Scale) 4 SCLK CS 3 04903-007 VDD 1 NC 4 AD7276/ AD7277/ AD7278 TOP VIEW (Not to Scale) 8 VIN 7 GND 6 SCLK 5 NC NC = NO CONNECT Figure 8. 6-Lead TSOT Pin Configuration 04903-008 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 9. 8-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions Pin No.
PAGE 14
AD7276/AD7277/AD7278 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 73.0 16,384 POINT FFT FSAMPLE = 3MSPS FIN = 1MHz SINAD = 71.2dB THD = –80.9dB SFDR = –82.4dB VDD = 3V –20 VDD = 3.6V 72.0 71.5 SNR (dB) SNR (dB) –40 72.5 –60 VDD = 3V 71.0 VDD = 2.35V 70.5 –80 70.0 –100 –120 0 04903-013 04903-009 69.5 69.0 100 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1000 Figure 13. AD7276 SNR vs.
PAGE 15
AD7276/AD7277/AD7278 1.0 –50 VDD = 3V 0.8 –55 0.6 DNL ERROR (LSB) RIN = 100Ω –60 THD (dB) –65 –70 RIN = 10Ω –75 0.4 0.2 0 –0.2 –0.4 –80 1000 04903-015 –90 100 –0.8 –1.0 1500 INPUT FREQUENCY (kHz) 1.0 VDD = 3V 0.6 0.2 0 –0.2 –0.4 –0.6 04903-011 INL ERROR (LSB) 0.4 –0.8 –1.0 0 500 1000 1500 2000 2500 3000 0 500 1000 1500 2000 2500 3000 CODE Figure 16. THD vs.
PAGE 16
AD7276/AD7277/AD7278 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7276/ AD7277/AD7278, the endpoints of the transfer function are zero scale at 0.5 LSB below the first code transition and full scale at 0.5 LSB above the last code transition. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental.
PAGE 17
AD7276/AD7277/AD7278 THEORY OF OPERATION CIRCUIT INFORMATION CHARGE REDISTRIBUTION DAC SW1 Figure 20. ADC Conversion Phase ADC TRANSFER FUNCTION The output coding of the AD7276/AD7277/AD7278 is straight binary. The designed code transitions occur midway between successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The LSB size is VDD/4,096 for the AD7276, VDD/1,024 for the AD7277, and VDD/256 for the AD7278. The ideal transfer characteristic for the AD7276/AD7277/AD7278 is shown in Figure 21.
PAGE 18
AD7276/AD7277/AD7278 3V 0.1µF 10µF VDD D1 VIN 5V SUPPLY REF193 1µF TANT Large source impedances significantly affect the ac performance of these ADCs and can necessitate the use of an input buffer amplifier. The AD8021 op amp is compatible with these devices; however, the choice of the op amp is a function of the particular application. C1 4pF 0.
PAGE 19
AD7276/AD7277/AD7278 MODES OF OPERATION The mode of operation of the AD7276/AD7277/AD7278 is selected by controlling the logic state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial power-down mode, and full power-down mode. The point at which CS is pulled high after the conversion has been initiated determines which power-down mode, if any, the device enters.
PAGE 20
AD7276/AD7277/AD7278 To exit this mode of operation and power up the AD7276/ AD7277/AD7278, users should perform a dummy conversion. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up once 16 SCLKs elapse; valid data results from the next conversion, as shown in Figure 26.
PAGE 21
AD7276/AD7277/AD7278 THE PART IS FULLY POWERED UP, SEE THE POWERUP TIMES SECTION THE PART BEGINS TO POWER UP CS 1 10 16 1 16 SCLK SDATA INVALID DATA 04903-026 A VALID DATA Figure 26. Exiting Partial Power-Down Mode THE PART ENTERS PARTIAL POWER-DOWN THE PART BEGINS TO POWER UP THE PART ENTERS FULL POWER-DOWN CS 1 2 10 16 1 10 16 THREE-STATE INVALID DATA SDATA 04903-027 SCLK THREE-STATE VALID DATA Figure 27.
PAGE 22
AD7276/AD7277/AD7278 50MHz SCLK VARIABLE SCLK 04903-029 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 THROUGHPUT (kSPS) Figure 29. Power vs. Throughput Normal Mode 8.0 VDD = 3V 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 04903-035 POWER (mW) Figure 29 shows the power consumption of the device in normal mode, in which the part is never powered down.
PAGE 23
AD7276/AD7277/AD7278 SERIAL INTERFACE Figure 31 through Figure 34 show the detailed timing diagrams for serial interfacing to the AD7276, AD7277, and AD7278. The serial clock provides the conversion clock and controls the transfer of information from the AD7276/AD7277/AD7278 during conversion. If 16 SCLKs are considered in the cycle, then the AD7278 clocks out six trailing zeros for the last six bits and SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 34.
PAGE 24
AD7276/AD7277/AD7278 t1 CS tCONVERT t2 t6 2 3 t3 SDATA THREESTATE Z B 4 5 13 DB11 DB10 DB9 15 16 t5 t7 t4 ZERO 14 t8 tQUIET DB1 DB0 ZERO 2 LEADING ZEROS ZERO THREE-STATE 2 TRAILING ZEROS 04903-030 1 SCLK 1/THROUGHPUT Figure 32.
PAGE 25
AD7276/AD7277/AD7278 AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE th For the AD7278, if CS is brought high during the 10 rising edge after the two leading zeros and eight bits of the conversion are provided, then the part can achieve a 4 MSPS throughput rate. For the AD7278, the track-and-hold goes back into track mode on the ninth rising edge. In this case, a fSCLK = 48 MHz and throughput of 4 MSPS result in a cycle time of t2 + 8.5(1/fSCLK) + tACQ = 250 ns, where t2 = 6 ns minimum and tACQ = 67 ns.
PAGE 26
AD7276/AD7277/AD7278 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7276/AD7277/ AD7278 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates using ground planes that can easily be separated. To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins of the AD7276/ AD7277/AD7278 should be sunk into the AGND plane.
PAGE 27
AD7276/AD7277/AD7278 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 2.80 BSC 1.60 BSC 1 3 2 PIN 1 INDICATOR 0.95 BSC 1.90 BSC *0.90 0.87 0.84 0.20 0.08 *1.00 MAX 8° 4° 0° SEATING PLANE 0.50 0.30 0.60 0.45 0.30 102808-A 0.10 MAX *COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 37. 6-Lead Thin Small Outline Transistor Package [TSOT] (UJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 3.20 3.00 2.80 8 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.
PAGE 28
AD7276/AD7277/AD7278 ORDERING GUIDE Model 1 AD7276BRM AD7276BRMZ AD7276BRMZ-REEL AD7276BUJZ-REEL7 Notes AD7276BUJZ-500RL7 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Linearity Error (LSB) 2 ±1 max ±1 max ±1 max ±1 max −40°C to +125°C ±1 max AD7276YUJZ-500RL7 3 −40°C to +125°C ±1 max AD7276YUJZ-REEL7 3 −40°C to +125°C ±1 max AD7276ARMZ AD7276ARMZ-REEL AD7276AUJZ- 500RL7 −40°C to +125°C −40°C to +125°C −40°C to +125°C ±1.5 max ±1.5 max ±1.