Datasheet

AD7273/AD7274
Rev. 0 | Page 8 of 28
TIMING EXAMPLES
For the AD7274, if
CS
is brought high during the 14
th
SCLK
rising edge after the two leading zeros and 12 bits of the
conversion are provided, the part can achieve the fastest
throughput rate, 3 MSPS. If
CS
is brought high during the 16
th
SCLK rising edge after the two leading zeros, 12 bits of the
conversion, and two trailing zeros are provided, a throughput
rate of 2.97 MSPS is achievable. This is illustrated in the
following two timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, f
SCLK
= 48 MHz, and
the throughput is 3 MSPS. This produces a cycle time of
t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 333 ns, where t
2
= 6 ns min and
t
ACQ
= 67 ns. This satisfies the requirement of 60 ns for t
ACQ
.
Figure 6 also shows that t
ACQ
comprises 0.5(1/f
SCLK
) + t
9
+ t
QUIET
,
where t
9
= 4.2 ns max. This allows a value of 52.8 ns for t
QUIET
,
satisfying the minimum requirement of 4 ns.
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, f
SCLK
= 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time
of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 336 ns, where t
2
= 6 ns min and
t
ACQ
= 70 ns. Figure 7 shows that t
ACQ
comprises 2.5(1/f
SCLK
) +
t
8
+ t
QUIET
, where t
8
= 14 ns max. This satisfies the minimum
requirement of 4 ns for t
QUIET.
12345 13141516
SCLK
S
DAT
A
THREE-STATETHREE-
STATE
TWO LEADING
ZEROS
TWO TRAILING
ZEROS
B
CS
t
3
t
CONVERT
t
2
ZEROZ DB11 DB10 DB9 DB1 DB0 ZERO ZERO
t
6
t
5
t
8
t
1
t
QUIET
1/THROUGHPUT
t
4
t
7
04973-005
Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle
12345 1314
SCLK
S
DAT
A
THREE-STATETHREE-
STATE
TWO LEADING
ZEROS
B
CS
t
3
t
CONVERT
t
2
ZEROZ DB11 DB10 DB9 DB1 DB0
t
6
t
9
t
1
t
QUIET
1/THROUGHPUT
t
4
t
7
04973-006
t
5
Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle
12345 1312 14 15 16
SCLK
B
CS
t
CONVERT
t
2
t
8
t
1
t
QUIET
1/THROUGHPUT
12.5(1/f
SCLK
) t
ACQUISITION
04973-007
Figure 7. Serial Interface Timing 16 SCLK Cycle