Datasheet

AD7273/AD7274
Rev. 0 | Page 7 of 28
TIMING SPECIFICATIONS
V
DD
= 2.35 V to 3.6 V; V
REF
= 2.35 to V
DD
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Guaranteed by characterization. All input signals
are specified with tr = tf = 2 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Table 4.
Parameter
Limit at T
MIN
, T
MAX
AD7273/AD7274
Unit Description
f
SCLK
2
500 kHz min
3
48 MHz max
t
CONVERT
14 × t
SCLK
AD7274
12 × t
SCLK
AD7273
t
QUIET
4 ns min
Minimum quiet time required between bus relinquish and start of
next conversion
t
1
3 ns min
Minimum
CS pulse width
t
2
6 ns min
CS to SCLK setup time
t
3
4
4 ns max
Delay from
CS until SDATA three-state disabled
t
4
4
15 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min SCLK low pulse width
t
6
0.4 t
SCLK
ns min SCLK high pulse width
t
7
4
5 ns min SCLK to data valid hold time
t
8
14 ns max SCLK falling edge to SDATA three-state
5 ns min SCLK falling edge to SDATA three-state
t
9
4.2 ns max
CS rising edge to SDATA three-state
t
POWER-UP
5
1 μs max Power-up time from full power-down
1
Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Minimum f
SCLK
at which specifications are guaranteed.
4
The time required for the output to cross the V
IH
or V
IL
voltage.
5
See the Power-Up Times section
SCLK
V
IH
V
IL
SDATA
t
4
04973-002
Figure 2. Access Time After SCLK Falling Edge
SCLK
V
IH
V
IL
SDATA
t
7
04973-003
Figure 3. Hold Time After SCLK Falling Edge
SCLK
1.4V
SDATA
t
8
04973-004
Figure 4. SCLK Falling Edge SDATA Three-State