Datasheet

AD7273/AD7274
Rev. 0 | Page 23 of 28
MICROPROCESSOR INTERFACING
AD7273/AD7274 to ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the
AD7273/AD7274 without requiring glue logic. The SPORT0
Receive Configuration 1 register should be set up as outlined in
Table 8.
AD7273/
AD7274
1
ADSP-BF53x
1
SCLK RCLK0
SPORT0
DR0PRI
RFS0
DT0
DOUT
CS
DIN
1
ADDITIONAL PINS OMITTED FOR CLARITY
04973-039
Figure 39. Interfacing to the ADSP-BF53x
Table 8. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
Setting Description
RCKFE = 1 Sample data with falling edge of RSCLK
LRFS = 1 Active low frame signal
RFSR = 1 Frame every word
IRFS = 1 Internal RFS used
RLSBIT = 0 Receive MSB first
RDTYPE = 00 Zero fill
IRCLK = 1 Internal receive clock
RSPEN = 1 Receive enabled
SLEN = 1111
16-bit data-word (or can be set to 1101 for a
14-bit data-word)
TFSR = RFSR = 1
To implement the power-down modes, set SLEN to 1001 to
issue an 8-bit SCLK burst.