Datasheet

AD7266
Rev. B | Page 22 of 28
SERIAL INTERFACE
Figure 41 shows the detailed timing diagram for serial inter-
facing to the AD7266. The serial clock provides the conversion
clock and controls the transfer of information from the AD7266
during conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once 13
SCLK falling edges have elapsed, the track-and-hold goes back
into track on the next SCLK rising edge, as shown in
at Point B. If a 16 SCLK transfer is used, then two trailing zeros
appear after the final LSB. On the rising edge of
Figure 41
CS
, the
conversion is terminated and D
OUT
A and D
OUT
B go back into
three-state. If
CS
is not brought high but is instead held low for a
further 14 (or 16) SCLK cycles on D
OUT
A, the data from
Conversion B is output on D
OUT
A (followed by two trailing zeros).
Likewise, if
CS
is held low for a further 14 (or 16) SCLK cycles
on D
OUT
B, the data from Conversion A is output on D
OUT
B. This
is illustrated in where the case for D
OUT
A is shown. In
this case, the D
OUT
line in use goes back into three-state on the
32
nd
SCLK falling edge or the rising edge of
Figure 42
CS
, whichever
occurs first.
A minimum of 14 serial clock cycles are required to perform
the conversion process and to access data from one conversion
on either data line of the AD7266.
CS
going low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first
falling clock edge on the serial clock has the leading zero
provided and also clocks out the second leading zero. The 12-bit
result then follows with the final bit in the data transfer valid on
the 14
th
falling edge, having being clocked out on the previous
(13
th
) falling edge. In applications with a slower SCLK, it may be
possible to read in data on each SCLK rising edge depending on
the SCLK frequency. The first rising edge of SCLK after the
CS
falling edge would have the second leading zero provided, and
the 13
th
rising SCLK edge would have DB0 provided.
Note that with fast SCLK values, and thus short SCLK periods,
in order to allow adequately for t
2
, an SCLK rising edge may
occur before the first SCLK falling edge. This rising edge of
SCLK may be ignored for the purposes of the timing
descriptions in this section. If a falling edge of SCLK is coincident
with the falling edge of
CS
, then this falling edge of SCLK is not
acknowledged by the AD7266, and the next falling edge of
SCLK will be the first registered after the falling edge of
CS
.
CS
SCLK
1
5
13
D
OUT
A
D
OUT
B
2 LEADING ZEROS
THREE-
STATE
t
4
2
34
t
5
t
3
t
QUIET
t
2
THREE-STATE
DB11
DB10
DB2
DB0
t
6
t
7
t
8
0
0
DB1
B
DB9 DB8
t
9
04603-034
Figure 41. Serial Interface Timing Diagram
CS
SCLK
1
5
15
D
OUT
A
THREE-
STATE
t
4
2
34
16
t
5
t
3
t
2
THREE-
STATE
t
6
t
7
14
ZERO0 ZERO
DB11
B
17
2 LEADING ZEROS
t
10
32
DB11
A
2 LEADING
ZEROS
DB10
A
DB9
A
ZEROZERO ZERO
2 TRAILING ZEROS
ZERO ZERO
2 TRAILING ZEROS
04603-035
Figure 42. Reading Data from Both ADCs on One D
OUT
Line with 32 SCLKs