Datasheet

AD7266
Rev. B | Page 17 of 28
The channels used for simultaneous conversions are selected via
the multiplexer address input pins, A0 to A2. The logic states of
these pins also need to be established prior to the acquisition
time; however, they may change during the conversion time
provided the mode is not changed. If the mode is changed from
fully differential to pseudo differential, for example, then the
acquisition time would start again from this point. The selected
input channels are decoded as shown in Table 6.
ANALOG INPUT SELECTION
The analog inputs of the AD7266 can be configured as single-
ended or true differential via the SGL/
DIFF
logic pin, as shown
in . If this pin is tied to a logic low, the analog input
channels to each on-chip ADC are set up as three true
differential pairs. If this pin is at logic high, the analog input
channels to each on-chip ADC are set up as six single-ended
analog inputs. The required logic level on this pin needs to be
established prior to the acquisition time and remain unchanged
during the conversion time until the track-and-hold has returned
to track. The track-and-hold returns to track on the 13
th
rising
edge of SCLK after the
Figure 31
CS
falling edge (see ). If the
level on this pin is changed, it will be recognized by the
AD7266; therefore, it is necessary to keep the same logic level
during acquisition and conversion to avoid corrupting the
conversion in progress.
Figure 41
The analog input range of the AD7266 can be selected as 0 V to
V
REF
or 0 V to 2 × V
REF
via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/
DIFF
pin by setting
the logic state of the RANGE pin a time t
acq
prior to the falling
edge of
CS
. Subsequent to this, the logic level on this pin can be
altered after the third falling edge of SCLK. If this pin is tied to a
logic low, the analog input range selected is 0 V to V
REF
. If this
pin is tied to a logic high, the analog input range selected is 0 V
to 2 × V
REF
.
For example, in Figure 31 the SGL/
DIFF
pin is set at logic high
for the duration of both the acquisition and conversion times so
the analog inputs are configured as single ended for that
conversion (Sampling Point A). The logic level of the SGL/
DIFF
changed to low after the track-and-hold returned to track and
prior to the required acquisition time for the next sampling
instant at Point B; therefore, the analog inputs are configured as
differential for that conversion.
OUTPUT CODING
The AD7266 output coding is set to either twos complement or
straight binary, depending on which analog input configuration
is selected for a conversion. Table 5 shows which output coding
scheme is used for each possible analog input configuration.
Table 5. AD7266 Output Coding
SGL/
DIFF
Range Output Coding
DIFF
SCLK
CS
114 141
A
SGL/DIFF
B
t
ACQ
04603-026
0 V to V
REF
Twos complement
DIFF 0 V to 2 × V
REF
Twos complement
SGL 0 V to V
REF
Straight binary
SGL 0 V to 2 × V
REF
Twos complement
PSEUDO DIFF 0 V to V
REF
Straight binary
PSEUDO DIFF
Figure 31. Selecting Differential or Single-Ended Configuration
0 V to 2 × V
REF
Twos complement
Table 6. Analog Input Type and Channel Selection
ADC A ADC B
SGL/
DIFF
A2 A1 A0
V
IN+
V
IN−
V
IN+
V
IN−
Comment
1 0 0 0 V
A1
AGND V
B1
AGND Single ended
1 0 0 1 V
A2
AGND V
B2
AGND Single ended
1 0 1 0 V
A3
AGND V
B3
AGND Single ended
1 0 1 1 V
A4
AGND V
B4
AGND Single ended
1 1 0 0 V
A5
AGND V
B5
AGND Single ended
1 1 0 1 V
A6
AGND V
B6
AGND Single ended
0 0 0 0 V
A1
V
A2
V
B1
V
B2
Fully differential
0 0 0 1 V
A1
V
A2
V
B1
V
B2
Pseudo differential
0 0 1 0 V
A3
V
A4
V
B3
V
B4
Fully differential
0 0 1 1 V
A3
V
A4
V
B3
V
B4
Pseudo differential
0 1 0 0 V
A5
V
A6
V
B5
V
B6
Fully differential
0 1 0 1 V
A5
V
A6
V
B5
V
B6
Pseudo differential