Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 32

Differential/Single-Ended Input, Dual

2 MSPS, 12-Bit, 3-Channel SAR ADC

AD7266

Rev. B

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FEATURES

Dual 12-bit, 3-channel ADC

Throughput rate: 2 MSPS

Specified for V

of 2.7 V to 5.25 V

Power consumption

9 mW at 1.5 MSPS with 3 V supplies

27 mW at 2 MSPS with 5 V supplies

Pin-configurable analog inputs

12-channel single-ended inputs

6-channel fully differential inputs

6-channel pseudo differential inputs

70 dB SNR at 50 kHz input frequency

Accurate on-chip reference: 2.5 V

±0.2% maximum @ 25°C, 20 ppm/°C maximum

Dual conversion with read 437.5 ns, 32 MHz SCLK

High speed serial interface

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

−40°C to +125°C operation

Shutdown mode: 1 μA maximum

32-lead LFCSP and 32-lead TQFP

1 MSPS version,

AD7265

GENERAL DESCRIPTION

The AD7266

is a dual, 12-bit, high speed, low power, successive

approximation ADC that operates from a single 2.7 V to 5.25 V

power supply and features throughput rates up to 2 MSPS. The

device contains two ADCs, each preceded by a 3-channel

multiplexer, and a low noise, wide bandwidth track-and-hold

amplifier that can handle input frequencies in excess of 30 MHz.

The conversion process and data acquisition use standard

control inputs allowing easy interfacing to microprocessors or

DSPs. The input signal is sampled on the falling edge of

;

conversion is also initiated at this point. The conversion time is

determined by the SCLK frequency. There are no pipelined

delays associated with the part.

The AD7266 uses advanced design techniques to achieve very

low power dissipation at high throughput rates. With 5 V

supplies and a 2 MSPS throughput rate, the part consumes

6.2 mA maximum. The part also offers flexible power/

throughput rate management when operating in normal mode

as the quiescent current consumption is so low.

The analog input range for the part can be selected to be a 0 V

to V

REF

(or 2 × V

REF

) range, with either straight binary or twos

complement output coding. The AD7266 has an on-chip 2.5 V

reference that can be overdriven when an external reference is

preferred. This external reference range is 100 mV to V

FUNCTIONAL BLOCK DIAGRAM

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

OUT

OUTPUT

DRIVERS

CONTROL

LOGIC

T/H

BUF

MUX

REF

AD7266

DRIVE

REF SELECT D

CAP

A AV

BUF

OUT

OUTPUT

DRIVERS

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

T/H

MUX

AGND AGND AGND D

CAP

B DGND DGND

SCLK

RANGE

SGL/DIFF

04603-001

Figure 1.

The AD7266 is available in a 32-lead LFCSP and a

32-lead TQFP.

PRODUCT HIGHLIGHTS

1. Two Complete ADC Functions Allow Simultaneous

Sampling and Conversion of Two Channels.

Each ADC has three fully/pseudo differential pairs, or six

single-ended channels, as programmed. The conversion

result of both channels is simultaneously available on

separate data lines, or in succession on one data line if only

one serial port is available.

2. High Throughput with Low Power Consumption.

The AD7266 offers a 1.5 MSPS throughput rate with 11.4 mW

maximum power dissipation when operating at 3 V.

3. The AD7266 offers both a standard 0 V to V

REF

input range

and a 2 × V

REF

input range.

4. No Pipeline Delay.

The part features two standard successive approximation

ADCs with accurate control of the sampling instant via a

input and once off conversion control.

Protected by U.S. Patent No. 6,681,332

Summary of content (29 pages)

PAGE 1
Differential/Single-Ended Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC AD7266 FEATURES FUNCTIONAL BLOCK DIAGRAM REF SELECT The conversion process and data acquisition use standard control inputs allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS; conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. There are no pipelined delays associated with the part.
PAGE 2
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PAGE 3
AD7266 TABLE OF CONTENTS Features .............................................................................................. 1 VDRIVE ............................................................................................ 18 General Description ......................................................................... 1 Modes of Operation ....................................................................... 19 Functional Block Diagram ...........................................................
PAGE 4
AD7266 SPECIFICATIONS TA = TMIN to TMAX, VDD = 2.7 V to 3.6 V, fSCLK = 24 MHz, fS = 1.5 MSPS, VDRIVE = 2.7 V to 3.6 V; VDD = 4.75 V to 5.25 V, fSCLK = 32 MHz, fS = 2 MSPS, VDRIVE = 2.7 V to 5.25 V; specifications apply using internal reference or external reference = 2.5 V ± 1%, unless otherwise noted1. Table 1.
PAGE 5
AD7266 Parameter DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT Reference Output Voltage8 Long-Term Stability Output Voltage Hysteresis2 Reference Input Voltage Range DC Leakage Current Input Capacitance DCAPA, DCAPB Output Impedance Reference Temperature Coefficient VREF Noise LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output
PAGE 6
AD7266 TIMING SPECIFICATIONS AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = TMAX to TMIN, unless otherwise noted1. Table 2. Parameter fSCLK2 tCONVERT tQUIET t2 t3 t43 t5 t6 t7 t8 t9 t10 Limit at TMIN , TMAX 1 4 32 14 × tSCLK 437.5 583.3 30 15/20 20/30 15 36 27 0.45 tSCLK 0.
PAGE 7
AD7266 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VDD to AGND DVDD to DGND VDRIVE to DGND VDRIVE to AGND AVDD to DVDD AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to GND VREF to AGND Input Current to Any Pin Except Supplies 1 Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP/TQFP θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Reflow Temperature (10 to 30 sec) ESD 1 Rating −0.3 V to +7 V −0.
PAGE 8
AD7266 AVDD 3 A0 CS SCLK AD7266 DCAP A 4 TOP VIEW (Not to Scale) A1 23 A2 22 SGL/DIFF 21 RANGE 20 DCAP B 19 AGND VA1 7 18 VB1 VA2 8 17 VB2 VB3 VB4 VB5 12 13 14 15 16 VB6 VA3 10 11 VA6 9 04603-002 24 AGND 6 AGND 5 VA3 VA4 VA5 VA6 VB6 VB5 VB4 VB3 NOTES 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE SHOULD BE SOLDERED TO PCB GROUND.
PAGE 9
AD7266 Pin No. 28, 30 Mnemonic DOUTB, DOUTA 31 VDRIVE 32 DVDD EPAD Description Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input and 14 SCLKs are required to access the data. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first.
PAGE 10
AD7266 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. –60 INTERNAL REFERENCE 4096 POINT FFT VDD = 5V, VDRIVE = 3V FSAMPLE = 2MSPS FIN = 52kHz SINAD = 71.4dB THD = –84.42dB DIFFERENTIAL MODE –10 –70 –30 –80 –50 (dB) PSRR (dB) EXTERNAL REFERENCE –90 –70 –100 200 400 600 800 1000 1200 1400 1600 1800 2000 SUPPLY RIPPLE FREQUENCY (kHz) –110 0 100 200 300 Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling 1.0 VDD = 5V 0.8 –60 0.6 –65 0.
PAGE 11
AD7266 1.0 0.8 NO. OF OCCURRENCES POSITIVE INL 0 –0.2 NEGATIVE INL –0.4 –0.6 5000 4000 3000 1.0 1.5 2.0 2.5 0 2046 2047 2048 2049 04603-012 0.5 04603-009 0 2050 CODE Figure 13. Histogram of Codes for 10k Samples in Differential Mode Figure 10. Linearity Error vs. VREF 10000 12.0 INTERNAL REFERENCE 9000 11.5 SINGLE-ENDED MODE 9984 CODES 8000 11.0 VDD = 5V SINGLE-ENDED MODE 10.5 NO. OF OCCURRENCES 10.0 VDD = 3V SINGLE-ENDED MODE 9.5 9.0 VDD = 3V DIFFERENTIAL MODE 8.
PAGE 12
AD7266 TERMINOLOGY Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
PAGE 13
AD7266 The AD7266 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second-order and third-order terms are specified separately.
PAGE 14
AD7266 THEORY OF OPERATION The AD7266 is a fast, micropower, dual, 12-bit, single-supply, ADC that operates from a 2.7 V to a 5.25 V supply. When operated from a 5 V supply, the AD7266 is capable of throughput rates of 2 MSPS when provided with a 32 MHz clock, and a throughput rate of 1.5 MSPS at 3 V. The AD7266 contains two on-chip, differential track-and-hold amplifiers, two successive approximation ADCs, and a serial interface with two separate data output pins.
PAGE 15
AD7266 VDD D R1 C2 VIN+ –50 D FSAMPLE = 1.5MSPS/2MSPS VDD = 3V/5V –55 RANGE = 0 TO VREF VDD –65 THD (dB) R1 C2 VIN– C1 VDD = 3V SINGLE-ENDED MODE –60 D 04603-015 D –70 VDD = 3V DIFFERENTIAL MODE –75 –80 Figure 18. Equivalent Analog Input Circuit, Conversion Phase—Switches Open, Track Phase—Switches Closed –85 When no amplifier is used to drive the analog input, the source impedance should be limited to low values.
PAGE 16
AD7266 3.5 The AD7266 can have a total of six differential analog input pairs. 3.0 COMMON-MODE RANGE (V) Differential Mode Differential signals have some benefits over single-ended signals, including noise immunity based on the device’s common-mode rejection and improvements in distortion performance. Figure 23 defines the fully differential analog input of the AD7266. VREF p-p VIN+ TA = 25°C 2.5 2.0 1.5 1.0 0.5 0 VIN– 0 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) 3.5 4.0 4.5 5.0 Figure 24.
PAGE 17
AD7266 Using an Op Amp Pair Pseudo Differential Mode An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7266. The circuit configurations illustrated in Figure 26 and Figure 27 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. The AD7266 can have a total of six pseudo differential pairs.
PAGE 18
AD7266 ANALOG INPUT SELECTION The analog inputs of the AD7266 can be configured as singleended or true differential via the SGL/DIFF logic pin, as shown in Figure 31. If this pin is tied to a logic low, the analog input channels to each on-chip ADC are set up as three true differential pairs. If this pin is at logic high, the analog input channels to each on-chip ADC are set up as six single-ended analog inputs.
PAGE 19
AD7266 TRANSFER FUNCTIONS DIGITAL INPUTS The designed code transitions occur at successive integer LSB values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB size is VREF/4096 when the 0 V to VREF range is used, and the LSB size is 2 × VREF/4096 when the 0 V to 2 × VREF range is used. In differential mode, the LSB size is 2 × VREF /4096 when the 0 V to VREF range is used, and the LSB size is 4 × VREF/4096 when the 0 V to 2 × VREF range is used.
PAGE 20
AD7266 MODES OF OPERATION The mode of operation of the AD7266 is selected by controlling the (logic) state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial powerdown mode, and full power-down mode. After a conversion is initiated, the point at which CS is pulled high determines which power-down mode, if any, the device enters.
PAGE 21
AD7266 Note that it is not necessary to complete the 14 SCLKs once CS is brought high to enter a power-down mode. FULL POWER-DOWN MODE This mode is intended for use in applications where throughput rates slower than those in the partial power-down mode are required, as power-up from a full power-down takes substantially longer than that from partial power-down.
PAGE 22
AD7266 THE PART BEGINS TO POWER UP. THE PART IS FULLY POWERED UP, SEE POWER-UP TIMES SECTION. tPOWER-UP2 CS DOUTA DOUTB 14 10 1 14 1 INVALID DATA 04603-033 SCLK VALID DATA Figure 38. Exiting Full Power-Down Mode TA = 25°C 9.5 9.0 8.5 VARIABLE SCLK 8.0 7.5 7.0 24MHz SCLK 6.5 6.0 5.5 5.0 0 200 400 600 800 1000 THROUGHPUT (kSPS) 1200 1400 04603-045 When power supplies are first applied to the AD7266, the ADC may power up in either of the power-down modes or normal mode.
PAGE 23
AD7266 SERIAL INTERFACE A minimum of 14 serial clock cycles are required to perform the conversion process and to access data from one conversion on either data line of the AD7266. CS going low provides the leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with a second leading zero. Thus, the first falling clock edge on the serial clock has the leading zero provided and also clocks out the second leading zero.
PAGE 24
AD7266 MICROPROCESSOR INTERFACING The serial interface on the AD7266 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7266 with some of the more common microcontroller and DSP serial interface protocols. AD7266 TO ADSP-218x The ADSP-218x family of DSPs interface directly to the AD7266 without any glue logic required. The VDRIVE pin of the AD7266 takes the same supply voltage as that of the ADSP-218x.
PAGE 25
AD7266 AD7266 TO ADSP-BF53x AD7266 TO TMS320C541 The ADSP-BF53x family of DSPs interface directly to the AD7266 without any glue logic required. The availability of secondary receive registers on the serial ports of the Blackfin® DSPs means only one serial port is necessary to read from both DOUT pins simultaneously. Figure 44 shows both DOUTA and DOUTB of the AD7266 connected to Serial Port 0 of the ADSP-BF53x.
PAGE 26
AD7266 The connection diagram in Figure 46 shows how the AD7266 can be connected to the ESSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. There are two on-board ESSIs, and each is operated in synchronous mode (Bit SYN = 1 in CRB register) with internally generated word length frame sync for both TX and RX (Bit FSL1 = 0 and Bit FSL0 = 0 in CRB). Normal operation of the ESSI is selected by making MOD = 0 in the CRB.
PAGE 27
AD7266 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP The analog and digital supplies to the AD7266 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The printed circuit board (PCB) that houses the AD7266 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates the use of ground planes that can be easily separated.
PAGE 28
AD7266 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 17 16 9 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 0.30 0.23 0.18 8 0.25 MIN 0.80 MAX 0.65 TYP SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 12° MAX 1 COPLANARITY 0.08 0.20 REF 011708-A TOP VIEW 1.00 0.85 0.