Datasheet

AD7265
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
AV
DD
= DV
DD
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, internal/external reference = 2.5 V, T
A
= T
MAX
to T
MIN
, unless otherwise noted
1
.
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
2
1 MHz min T
A
= −40°C to +85°C
4 MHz min T
A
> 85°C to 125°C
16 MHz max
t
CONVERT
14 × t
SCLK
ns max t
SCLK
= 1/f
SCLK
875 ns max f
SCLK
= 16 MHz
t
QUIET
30 ns min
Minimum time between end of serial read and next falling edge of
CS
t
2
15/20 ns min
V
DD
= 5 V/3 V, CS to SCLK setup time, T
A
= −40°C to +85°C
20/30 ns min
V
DD
= 5 V/3 V, CS to SCLK setup time, T
A
> 85°C to 125°C
t
3
15 ns max
Delay from
CS until D
OUT
A and D
OUT
B are three-state disabled
t
4
3
36 ns max Data access time after SCLK falling edge, V
DD
= 3 V
27 ns max Data access time after SCLK falling edge, V
DD
= 5 V
t
5
0.45 t
SCLK
ns min SCLK low pulse width
t
6
0.45 t
SCLK
ns min SCLK high pulse width
t
7
10 ns min SCLK to data valid hold time, V
DD
= 3 V
5 ns min SCLK to data valid hold time, V
DD
= 5 V
t
8
15 ns max
CS rising edge to D
OUT
A, D
OUT
B, high impedance
t
9
30 ns min
CS rising edge to falling edge pulse width
t
10
5 ns min SCLK falling edge to D
OUT
A, D
OUT
B, high impedance
50 ns max SCLK falling edge to D
OUT
A, D
OUT
B, high impedance
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Serial
Interface section and Figure 41 and Figure 42.
2
Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.
3
The time required for the output to cross 0.4 V or 2.4 V.