Datasheet

AD7265
Rev. A | Page 4 of 28
Parameter Specification Unit Test Conditions/Comments
DC Leakage Current ±1 μA max
Input Capacitance 45 pF typ When in track
10 pF typ When in hold
REFERENCE INPUT/OUTPUT
Reference Output Voltage
8
2.5 V min/V max ±0.2% max @ 25°C
Long-Term Stability 150 ppm typ For 1000 hours
Output Voltage Hysteresis
2
50 ppm typ
Reference Input Voltage Range 0.1/V
DD
V min/V max See Typical Performance Characteristics section
DC Leakage Current ±2 μA max External reference applied to Pin D
CAP
A/Pin D
CAP
B
Input Capacitance 25 pF typ
D
CAP
A, D
CAP
B Output Impedance 10 Ω typ
Reference Temperature Coefficient 20 ppm/°C max
10 ppm/°C typ
V
REF
Noise 20 μV rms typ
LOGIC INPUTS
Input High Voltage, V
INH
2.8 V min
Input Low Voltage, V
INL
0.4 V max
Input Current, I
IN
±15 nA typ V
IN
= 0 V or V
DRIVE
Input Capacitance, C
IN
3
5 pF typ
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DRIVE
− 0.2 V min
Output Low Voltage, V
OL
0.4 V max
Floating State Leakage Current ±1 μA max
Floating State Output Capacitance
3
7 pF typ
Output Coding
Straight (natural) binary
SGL/
DIFF = 1 with 0 V to V
REF
range selected
Twos complement
SGL/
DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × V
REF
range
CONVERSION RATE
Conversion Time 14 SCLK cycles 875 ns with SCLK = 16 MHz
Track-and-Hold Acquisition Time
3
90 ns max Full-scale step input; V
DD
= 5 V
110 ns max Full-scale step input; V
DD
= 3 V
Throughput Rate 1 MSPS max
POWER REQUIREMENTS
V
DD
2.7/5.25 V min/V max
V
DRIVE
2.7/5.25 V min/V max
I
DD
Digital I/Ps = 0 V or V
DRIVE
Normal Mode (Static) 2.3 mA max V
DD
= 5.25 V
Operational, f
S
= 1 MSPS 4 mA max V
DD
= 5.25 V; 3.5 mA typ
f
S
= 1 MSPS 3.2 mA max V
DD
= 3.6 V; 2.7 mA typ
Partial Power-Down Mode 500 μA max Static
Full Power-Down Mode (V
DD
) 1 μA max T
A
= −40°C to +85°C
2.8 μA max T
A
> 85°C to 125°C
Power Dissipation
Normal Mode (Operational) 21 mW max V
DD
= 5.25 V
Partial Power-Down (Static) 2.625 mW max V
DD
= 5.25 V
Full Power-Down (Static) 5.25 μW max V
DD
= 5.25 V, T
A
= −40°C to +85°C
1
Temperature range is −40°C to +125°C.
2
See Terminology section.
3
Sample tested during initial release to ensure compliance.
4
Guaranteed no missed codes to 12 bits.
5
V
IN−
or V
IN+
must remain within GND/V
DD
.
6
V
IN−
= 0 V for specified performance. For full input range on V
IN−
pin, see Figure 28 and Figure 29.
7
For full common-mode range, see Figure 24 and Figure 25.
8
Relates to Pin D
CAP
A or Pin D
CAP
B.