Datasheet

AD7265
Rev. A | Page 19 of 28
MODES OF OPERATION
Once 32 SCLK cycles have elapsed, the D
The mode of operation of the AD7265 is selected by controlling
the (logic) state of the
OUT
line returns to
three-state on the 32
CS
signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. After a conversion is
initiated, the point at which
CS
SCLK falling edge. If
nd
is brought high
prior to this, the D
OUT
line returns to three-state at that point.
Therefore,
CS
may idle low after 32 SCLK cycles until it is
brought high again sometime prior to the next conversion
(effectively idling
CS
is pulled high determines which
power-down mode, if any, the device enters. Similarly, if already
in a power-down mode,
CS
low), if so desired, because the bus still
returns to three-state upon completion of the dual result read.
CS
can control whether the device
returns to normal operation or remains in power-down. These
modes of operation are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for differing
application requirements.
Once a data transfer is complete and D
A and D
OUT OUT
B have
returned to three-state, another conversion can be initiated after
the quiet time, t
CS
NORMAL MODE
This mode is intended for applications that need the fastest
throughput rates because the user does not have to worry about
any power-up times with the AD7265 remaining fully powered
at all times.
Figure 34 shows the general diagram of the
operation of the AD7265 in this mode.
SCLK
LEADING ZEROS + CONVERSION RESULT
CS
D
OUT
A
D
OUT
B
110 14
04674-029
Figure 34. Normal Mode Operation
The conversion is initiated on the falling edge of
CS
, as
described in the
Serial Interface section. To ensure that the part
remains fully powered up at all times,
CS
must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of
CS
. If
CS
is brought high any time after the 10
th
SCLK falling
edge but before the 14
th
SCLK falling edge, the part remains
powered up, but the conversion is terminated and D
OUT
A and
D
OUT
B go back into three-state. Fourteen serial clock cycles are
required to complete the conversion and access the conversion
result. The D
OUT
line does not return to three-state after 14
SCLK cycles have elapsed, but instead does so when
CS
is
brought high again. If
CS
is left low for another 2 SCLK cycles
(for example, if only a 16 SCLK burst is available), two trailing
zeros are clocked out after the data. If
CS
is left low for a further
14 (or 16) SCLK cycles, the result from the other ADC on board
is also accessed on the same D
OUT
line, as shown in Figure 42
(see the
Serial Interface section).
QUIET
, has elapsed by bringing low again
(assuming the required acquisition time is allowed).
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate, and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7265 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffer.
To enter partial power-down mode, the conversion process
must be interrupted by bringing
CS
high anywhere after the
second falling edge of SCLK and before the 10
th
falling edge of
SCLK, as shown in
CS
Figure 35. Once is brought high in this
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of
CS
is
terminated, and D
OUT
A and D B go back into three-state. If
OUT
CS
is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the
CS
line.
SCLK
THREE-STATE
CS
D
OUT
A
D
OUT
B
1110 42
04674-030
Figure 35. Entering Partial Power-Down Mode