Datasheet

AD7264 Data Sheet
Rev. B | Page 6 of 28
TIMING SPECIFICATIONS
AV
CC
= 4.75 V to 5.25 V, C
A
_C
B
V
CC
= C
C
_C
D
V
CC
= 2.7 V to 5.25 V, V
REF
= 2.5 V internal/external; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 2.
Limit at T
MIN
, T
MAX
Parameter 2.7 V ≤ V
DRIVE
≤ 3.6 V 4.75 V ≤ V
DRIVE
≤ 5.25 V Unit Description
f
SCLK
200 200 kHz min
34 34
2
MHz max AD7264
20 20 MHz max AD7264-5
t
CONVERT
19 × t
SCLK
19 × t
SCLK
ns max t
SCLK
= 1/f
SCLK
560 560 ns max AD7264
950 950 ns max AD7264-5
t
QUIET
13
13
ns min
Minimum time between end of serial read/bus relinquish
and next falling edge of
CS
t
2
10 10 ns min
CS
to SCLK setup time
t
3
3
15 15 ns max Delay from 19
th
SCLK falling edge until D
OUT
A and D
OUT
B are
three-state disabled
t
4
29 23 ns max Data access time after SCLK falling edge
t
5
15 13 ns min SCLK to data valid hold time
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK high pulse width
t
7
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK low pulse width
t
8
13 13 ns min
CS
rising edge to falling edge pulse width
t
9
13 13 ns max
CS
rising edge to D
OUT
A, D
OUT
B high impedance/bus
relinquish
t
10
5 5 ns min SCLK falling edge to D
OUT
A, D
OUT
B high impedance
35 35 ns max SCLK falling edge to D
OUT
A, D
OUT
B high impedance
t
11
2
2
μs min
Minimum CAL pin high time
t
12
2 2 μs min Minimum time between the CAL pin high and the
CS
falling edge
t
13
3 3 ns min D
IN
setup time prior to SCLK falling edge
t
14
3 3 ns min D
IN
hold time after SCLK falling edge
t
POWER-UP
240 240 μs max Internal reference, with a 1 μF decoupling capacitor
15 15 μs max With an external reference, 10 μs typical
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
Terminology section.
2
The AD7264 is functional with a 40 MHz SCLK at 25°C, but specified performance is not guaranteed with SCLK frequencies greater than 34 MHz.
3
The time required for the output to cross 0.4 V or 2.4 V.
CS
SCLK
1 5 19
D
OUT
A
THREE-STATE
t
4
2 3 4 20
t
5
THREE-
STATE
t
7
t
3
18
DB11
A
DB12
A
DB13
A
21 31 32 33
DB1
A
DB0
A
D
OUT
B
THREE-STATE
THREE-
STATE
DB11
B
DB12
B
DB13
B
DB1
B
DB0
B
06732-002
t
2
t
9
t
8
t
QUIET
t
6
Figure 2. Serial Interface Timing Diagram