Datasheet

AD7264 Data Sheet
Rev. B | Page 24 of 28
CS
SCLK
1 5 19
D
OUT
A
THREE-STATE
t
4
2 3 4 20
t
5
THREE-
STATE
18
DB11
A
DB12
A
DB13
A
21 22 31 32 33
DB1
A
DB0
A
D
OUT
B
THREE-STATE
THREE-
STATE
DB11
B
DB12
B
DB13
B
DB1
B
DB0
B
06732-039
t
2
t
8
FIRST DATA BIT CLOCKED
OUT ON THIS EDGE
FIRST DATA BIT READ
ON THIS EDGE
Figure 35. Serial Interface Timing Diagram When Reading Data on the Rising SCLK Edge with V
DRIVE
= 3 V