Datasheet

Data Sheet AD7264
Rev. B | Page 23 of 28
SERIAL INTERFACE
Figure 33 and Figure 34 show the detailed timing diagrams for
the serial interface on the AD7264. The serial clock provides the
conversion clock and controls the transfer of information from
the AD7264 after the conversion. The AD7264 has two output
pins corresponding to each ADC. Data can be read from the
AD7264 using both D
OUT
A and D
OUT
B. Alternatively, a single
output pin of the user’s choice can be used. The SCLK input
signal provides the clock source for the serial interface.
The falling edge of
CS
puts the track-and-hold into hold mode,
at which point the analog input is sampled. The conversion is
also initiated at this point and requires a minimum of 19 SCLK
cycles to complete. The D
OUT
x lines remain in three-state while
the conversion is taking place. On the 19
th
SCLK falling edge, the
AD7264 returns to track mode and the D
OUT
A and D
OUT
B lines
are enabled. The data stream consists of 14 bits of data, MSB first.
The MSB of the conversion result is clocked out on the 19
th
SCLK falling edge to be read by the microcontroller or DSP on
the subsequent SCLK falling edge (the 20
th
falling edge). The
remaining data is then clocked out by subsequent SCLK falling
edges. Thus, the 20
th
falling clock edge on the serial clock has
the MSB provided and also clocks out the second data bit. The
remainder of the 14-bit result follows, with the final bit in the
data transfer being valid for reading on the 33
rd
falling edge.
The LSB is provided on the 32
nd
falling clock edge.
The AD7264-5, with its 20 MHz SCLK frequency, easily
facilitates reading on the SCLK falling edge. When using a
V
DRIVE
voltage of 5 V with the AD7264, the maximum specified
access time (t
4
) is 23 ns, which enables reading on the subse-
quent falling SCLK edge after the data has been clocked out, as
described previously. However, if a V
DRIVE
voltage of 3 V is used
for the AD7264 and the setup time of the microcontroller or
DSP is too large to enable reading on the falling SCLK edge, it
may be necessary to read on the SCLK rising edge. In this case,
the MSB of the conversion result is clocked out on the 19
th
SCLK
falling edge to be read on the 20
th
SCLK rising edge, as shown in
Figure 35. This is possible because the hold time (t
5
) is longer for
lower V
DRIVE
voltages. If the data access time is too long to accom-
modate the setup time of the chosen processor, an alternative to
reading on the rising SCLK edge is to use a slower SCLK frequency.
On the rising edge of
CS
, D
OUT
A and D
OUT
B go back into three-
state. If
CS
is not brought high after 33 SCLK cycles but is instead
held low for an additional 14 SCLK cycles, the data from ADC B
is output on D
OUT
A after the ADC A result. Likewise, the data
from ADC A is output on D
OUT
B after the ADC B result. This is
illustrated in
Figure 34, which shows the D
OUT
A example. In this
case, the D
OUT
line in use goes back into three-state on the 47
th
SCLK falling edge or the rising edge of
CS
, whichever occurs first.
If the falling edge of SCLK coincides with the falling edge of
CS
,
the falling edge of SCLK is not acknowledged by the AD7264,
and the next falling edge of SCLK is the first one registered after
the falling edge of
CS
.
CS
SCLK
1
5
19
D
OUT
A
THREE-STATE
t
4
2
3 4
20
t
5
THREE-
STATE
t
7
t
3
18
DB11
A
DB12
A
DB13
A
21 31 32
33
DB1
A
DB0
A
D
OUT
B
THREE-STATE
THREE-
STATE
DB11
B
DB12
B
DB13
B
DB1
B
DB0
B
06732-033
t
2
t
9
t
8
t
QUIET
t
6
FIRST DATA BIT CLOCKED
OUT ON THIS EDGE
FIRST DATA BIT READ
ON THIS EDGE
Figure 33. Normal Mode Operation
06732-034
CS
32 333121201918
D
OUT
A
THREE-STATE
THREE-
STATE
SCLK
1 2
45 46 47
DB13
A
DB12
A
DB1
A
DB0
A
DB13
B
DB12
B
DB1
B
DB0
B
t
10
Figure 34. Reading Data from Both ADCs on One D
OUT
Line with 47 SCLK Cycles