Datasheet

AD7264 Data Sheet
Rev. B | Page 22 of 28
ON-CHIP REGISTERS
The AD7264 contains a control register, two offset registers for
storing the offsets for each ADC, and two external gain registers
for storing the gain error. The control, offset, and gain registers
are read and write registers. On power-up, all registers in the
AD7264 are set to 0 by default.
Writing to a Register
Data is loaded from the PD0/D
IN
pin of the AD7264 on the
falling edge of SCLK when
CS
is in a logic low state. Four
address bits and 12 data bits must be clocked into the device.
Thus, on the 16
th
falling SCLK edge, the LSB is clocked into the
AD7264. One more SCLK cycle is then required to write to the
internal device registers. In total, 17 SCLK cycles are required to
successfully write to the AD7264. The control and offset registers
are 12-bits registers, and the gain registers are 7-bit registers.
When writing to a register, the user must first write the address
bits corresponding to the selected register. Table 11 shows the
decoding of the address bits. The four RD bits are written MSB
first, that is, RD3 followed by RD2, RD1, and RD0. The AD7264
decodes these bits to determine which register is being addressed.
The subsequent 12 bits of data are written to the addressed register.
When writing to the external gain registers, the seven bits of data
immediately after the four address bits are written to the register.
However, 17 SCLK cycles are still required, and the PD0/D
IN
pin of
the AD7264 should be tied low for the five additional clock cycles.
Table 11. Read and Write Register Addresses
RD3 RD2 RD1 RD0 Comment
0 0 0 0 ADC result (default)
0 0 0 1 Control register
0 0 1 0 Offset ADC A internal
0 0 1 1 Offset ADC B internal
0 1 0 0 Gain ADC A external
0 1 0 1 Gain ADC B external
Reading from a Register
The internal offset of the device, which has been measured by
the AD7264 and stored in the on-chip registers during the
calibration, can be read back by the user. The contents of the
external gain registers can also be read. To read the contents of
any register, the user must first write to the control register by
writing 0001 to the WR3 to WR0 bits via the PD0/D
IN
pin (see
Table 10). The next four bits in the control register are the RD
bits, which are used to select the desired register from which to
read. The appropriate 4-bit addresses for each of the offset and
gain registers are listed in Table 11. The remaining eight SCLK
cycle bits are used to set the remaining bits in the control
register to the desired state for the next ADC conversion.
The 19
th
SCLK falling edge clocks out the first data bit of the
digital code corresponding to the value stored in the selected
internal device register on the D
OUT
A pin. D
OUT
B outputs the
conversion result from ADC B. When the selected register has
been read, the control register must be reset to output the ADC
results for future conversions. This is achieved by writing 0001
to the WR3 to WR0 bits, followed by 0000 to the RD bits. The
remaining eight bits in the control register should then be set to
the required configuration for the next ADC conversion.
06732-031
CS
SCLK
D
OUT
A
PD0/D
IN
10 14 16
THREE-STATE
11 12 13 17
THREE-
STATE
15
DB12
A
DB13
A
18
2019 32 33
DB0
A
THREE-STATE
RD1 RD0 MSB DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0RD2RD3
t
2
t
8
t
QUIET
987654321
t
13
t
14
Figure 31. Timing Diagram for Writing to a Register
06732-032
CS
SCLK
D
OUT
A
PD0/D
IN
10 14 16
THREE-STATE
11 12 13 17
THREE-
STATE
15
DB12
A
DB13
A
18
2019 32 33
DB0
A
THREE-STATE
0 1 RD3 RD2 RD1 RD0 0 0 0 0 0 0 0 000
t
2
t
13
t
14
t
8
t
QUIET
987654321
Figure 32. Timing Diagram for a Read Operation with PD0/D
IN
as an Input