Datasheet
Data Sheet AD7264
Rev. B | Page 17 of 28
TYPICAL CONNECTION DIAGRAMS
Figure 26 and Figure 27 are typical connection diagrams for the
AD7264. In these configurations, the AGND pin is connected
to the analog ground plane of the system, and the DGND pin is
connected to the digital ground plane of the system. The analog
inputs on the AD7264 are true differential and have an input
impedance in excess of 1 GΩ; thus, no driving op amps are
required. The AD7264 can operate with either an internal or an
external reference. In Figure 26, the AD7264 is configured to
operate in control register mode; thus, G0 to G3, PD1, and PD2
can be connected to ground (low logic state). Figure 27 has the
gain pins configured for a gain of 2 setup; thus, the device is in
pin driven mode. Both circuit configurations illustrate the use
of the internal 2.5 V reference.
The C
A
_C
B
V
CC
and C
C
_C
D
V
CC
pins can be connected to either a
3 V or 5 V supply voltage. The AV
CC
pin must be connected to
a 5 V supply. All supplies should be decoupled with a 100 nF
capacitor at the device pin, and some supply sources may
require a 10 μF capacitor where the source is supplied to the
circuit board. The V
DRIVE
pin is connected to the supply voltage
of the microprocessor. The voltage applied to the V
DRIVE
input
controls the voltage of the serial interface. V
DRIVE
can be set to
3 V or 5 V.
10µF
1
100nF
V
DRIVE
V
DRIVE
3V OR 5V
SUPPLY
MICROPROCESSOR/
MICROCONTROLLER
10µF
1
COMPARATOR
SUPPLY 3V TO 5V
2
100nF
100nF
100nF
ANALOG
SUPPLY
+5V
10µF
1
100nF
100nF
100nF
100nF
100nF
C
C+
C
C–
C
D+
C
D–
C
B–
C
B+
C
A–
C
A+
C
OUT
D
C
OUT
C
C
OUT
B
C
OUT
A
V
DRIVE
G0
G1
G2
G3
SCLK
D
OUT
A
D
OUT
B
REFSEL
CAL
PD0/D
IN
PD1
PD2
13 14 15 16 45 46 47 48 25 26 29 30
22
23
06732-026
36
24
32
35
34
37
38
39
40
27
31
21
3.125V
V
A–
AND V
A+
CONNECT
DIRECTLY
TO SENSOR
OUTPUTS
THIS REFERENCE SIGNAL
MUST BE BUFFERED
BEFORE IT CAN BE
USED ELSEWHERE IN
THE CIRCUIT
2.500V
1.875V
GAIN 2
3.125V
2.500V
1.875V
GAIN 2
3.125V
2.500V
1.875V
GAIN 2
3.125V
2.500V
1.875V
GAIN 2
V
B–
AND V
B+
CONNECT
DIRECTLY
TO SENSOR
OUTPUTS
1µF
1µF
C
C–
C
D–
GND
C
A–
C
B–
GND
C
C–
C
D
V
CC
C
A–
C
B
V
CC
AGND
AGND
AGND
AGND
AGND
DGND
AV
CC
AV
CC
AV
CC
AV
CC
AV
CC
AV
CC
17 44 5 6 8 19 42 28 2 7 11 20 41 12 1 33
V
B–
V
B+
V
REF
B
V
REF
A
V
A+
V
A–
10
9
18
43
4
3
AD7264
FAST PROPAGATION DELAY
COMPARATOR INPUTS
1
THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED IN ALL SYSTEMS.
2
THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED.
LOW POWER
COMPARATOR INPUTS
SERIAL
INTERFACE
CS
Figure 26. Typical Connection Diagram for the AD7264 in Control Register Mode (All Gain Pins Tied to Ground) Configured for a PGA Gain of 2