Datasheet

AD7264 Data Sheet
Rev. B | Page 16 of 28
06732-024
C1
V
IN
–
V
DD
C1
V
IN
+
V
OUT
–
V
OUT
+
V
DD
AMP
AMP
Figure 24. Analog Input Structure
The AD7264 can accept differential analog inputs from






×
−
Gain2
V
V
REF
CM
to






×
+
Gain2
V
V
REF
CM
.
Table 5 details the analog input range for the AD7264 for the
various PGA gain settings. V
REF
= 2.5 V and V
CM
= 2.5 V
(AV
CC
/2, with AV
CC
= 5 V).
Table 5. Analog Input Range for Various PGA Gain Settings
PGA Gain Setting Analog Input Range for V
IN
+ and V
IN
−
1 0.75 V to 3.25 V
1
2 1.875 V to 3.125 V
3 2.083 V to 2.916 V
4 2.187 V to 2.813 V
6 2.292 V to 2.708 V
8 2.344 V to 2.656 V
12 2.396 V to 2.604 V
16 2.422 V to 2.578 V
24
2.448 V to 2.552 V
32 2.461 V to 2.539 V
48 2.474 V to 2.526 V
64 2.480 V to 2.520 V
96 2.487 V to 2.513 V
128
2.490 V to 2.510 V
1
For V
CM
= 2 V. If V
CM
= AV
CC
/2, the analog input range for V
IN
+ and V
IN
− is 1.6 V
to 3.4 V.
When a full-scale step input is applied to either differential
input on the AD7264 while the other analog input is held at a
constant voltage, 3 μs of settling time is typically required prior
to capturing a stable digital output code.
Transfer Function
The AD7264 output is twos complement; the ideal transfer
function is shown in Figure 25. The designed code transitions
occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and
so on). The LSB size is dependent on the analog input range
selected.
The LSB size for the AD7264 is




























×
−−














×
+
×
384,16
22
2
Gain
V
V
Gain
V
V
REF
CM
REF
CM
06732-025
100...000
011...111
ADC CODE
0V
100...001
100...010
011...110
000...001
111...111
000...000
ANALOG INPUT
NOTES
1. FULL-SCALE RANGE (FSR) = V
IN
+ – V
IN
–.
(V
CM
+ (FSR/2)) – 1LSB(V
CM
– (FSR/2)) + 1LSB
Figure 25. Twos Complement Transfer Function
V
DRIVE
The AD7264 has a V
DRIVE
feature to control the voltage at which
the serial interface operates. V
DRIVE
allows the ADC and the
comparators to easily interface to both 3 V and 5 V processors.
For example, when the AD7264 is operated with AV
CC
= 5 V, t h e
V
DRIVE
pin can be powered from a 3 V supply, allowing a large
analog input range with low voltage digital processors.
REFERENCE
The AD7264 can operate with either the internal 2.5 V on-chip
reference or an externally applied reference. The logic state of
the REFSEL pin determines whether the internal reference is
used. The internal reference is selected for both ADCs when the
REFSEL pin is tied to logic high. If the REFSEL pin is tied to
AGND, an external reference can be supplied through the V
REF
A
and/or V
REF
B pins. On power-up, the REFSEL pin must be tied to
either a low or high logic state for the part to operate. Suitable
reference sources for the AD7264 include the AD780, AD1582,
ADR431, REF193, and ADR391.
The internal reference circuitry consists of a 2.5 V band gap refer-
ence and a reference buffer. When operating the AD7264 in
internal reference mode, the 2.5 V internal reference is available at
the V
REF
A and V
REF
B pins, which should be decoupled to AGND
using a 1 μF capacitor. It is recommended that the internal refer-
ence be buffered before applying it elsewhere in the system. The
internal reference is capable of sourcing up to 90 μA of current
when the converter is static. If internal reference operation is
required for the ADC conversion, the REFSEL pin must be tied
to logic high on power-up. The reference buffer requires 240 µs
to power up and charge the 1 μF decoupling capacitor during
the power-up time.