Datasheet

–4–
AD7249
PIN FUNCTION DESCRIPTION (DIP & SOIC PIN NUMBERS)
Pin Mnemonic Description
11 REFOUT Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the
part using its internal reference, REFOUT should be connected to REFIN.
12 REFIN Voltage Reference Input. It is internally buffered before being applied to both DACs. The nominal
reference voltage for specified operation of the AD7249 is 5 V.
13R
OFSB
Output Offset Resistor for the amplifier of DAC B. It is connected to V
OUTB
for the +5 V range, to
AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
14V
OUTB
Analog Output Voltage of DAC B. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
15 AGND Analog Ground. Ground reference for all analog circuitry.
16 CLR Clear, Logic Input. Taking this input low clears both DACs. It sets V
OUTA
and V
OUTB
to 0 V in both
unipolar ranges and the twos complement bipolar range and to –REFIN in the offset binary bipolar
range.
17 BIN/COMP Logic Input. This input selects the data format to be either binary or twos complement. In both uni-
polar ranges natural binary format is selected by connecting this input to a Logic “0”. In the bipolar
configuration offset binary format is selected with a Logic “0” while a Logic “1” selects twos complement.
18 DGND Digital Ground. Ground reference for all digital circuitry.
19 SDIN Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
10 LDAC Load DAC, Logic Input. Updates both DAC outputs. The DAC outputs are updated on the falling
edge of this signal or alternatively if this line is permanently low, an automatic update mode is se-
lected whereby both DACs are updated on the 16th falling SCLK pulse.
11 SCLK Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
12 SYNC Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readi-
ness for a new data word.
13 V
DD
Positive Power Supply.
14 V
OUTA
Analog Output Voltage of DAC A. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
15 V
SS
Negative Power Supply (used for the output amplifier only) may be connected to 0 V for single sup-
ply operation or –12 V to –15 V for dual supplies.
16 R
OFSA
Output Offset Resistor for the amplifier of DAC A. It is connected to V
OUTA
for the +5 V range, to
AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
PIN CONFIGURATIONS
(DIP and SOIC)
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
REFOUT R
OFSA
AD7249
REFIN V
SS
R
OFSB
V
OUTA
V
OUTB
V
DD
AGND
SYNC
CLR
SCLK
BIN/COMP LDAC
DGND SDIN
REV. D