Datasheet

REV. B
–2–
AD7233–SPECIFICATIONS
1
(V
DD
= +12 V to +15 V,
2
V
SS
= –12 V to –15 V,
2
GND = 0 V, R
L
= 2 k⍀, C
L
= 100 pF
to GND. All specifications T
MIN
to T
MAX
unless otherwise noted.)
P arameter A Version B Version Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 12 12 Bits
Relative Accuracy
3
± 1 ± 1/2 LSB max
Differential Nonlinearity
3
± 0.9 ± 0.9 LSB max Guaranteed Monotonic
Bipolar Zero Error
3
± 6 ± 6 LSB max DAC Latch Contents 0000 0000 0000
Full-Scale Error
3
± 8 ± 8 LSB max
Full-Scale Temperature Coefficient
4
± 30 ± 30 ppm of FSR/°C typ Guaranteed By Process
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 V max
Input Current
I
IN
± 1 ± 1 µA max V
IN
= 0 V to V
DD
Input Capacitance
4
8 8 pF max
ANALOG OUTPUTS
Output Voltage Range ± 5 ± 5V
DC Output Impedance
4
0.5 0.5 Ω typ
AC CHARACTERISTICS
4
Voltage Output Settling Time Settling Time to Within ± 1/2 LSB of Final Value
Positive Full-Scale Change 10 10 µs max Typically 4 µs; DAC Latch 100. . .000 to 011. . .111
Negative Full-Scale Change 10 10 µs max Typically 5 µs; DAC Latch 011. . .111 to 100. . .000
Digital-to-Analog Glitch Impulse
3
30 30 nV secs typ DAC Latch Contents Toggled Between All 0s and all 1s
Digital Feedthrough
3
10 10 nV secs typ LDAC = High
POWER REQUIREMENTS
V
DD
Range 10.8/16.5 10.8/16.5 V min/V max For Specified Performance Unless Otherwise Stated
V
SS
Range –10.8/–16.5 –10.8/–16.5 V min/V max For Specified Performance Unless Otherwise Stated
I
DD
10 10 mA max Output Unloaded; Typically 7 mA at Thresholds
I
SS
2 2 mA max Output Unloaded; Typically 1 mA at Th resholds
NOTES
1
Temperature Ranges are as follows: A, B Versions: –40°C to +85°C.
2
Power Supply Tolerance: A, B Versions: ± 10%.
3
See Terminology.
4
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
Limit at 25ⴗC, T
MIN
, T
MAX
Parameter (All Versions) Unit Conditions/Comments
t
1
3
200 ns min SCLK Cycle Time
t
2
15 ns min SYNC to SCLK Falling Edge Setup Time
t
3
70 ns min SYNC to SCLK Hold Time
t
4
0 ns min Data Setup Time
t
5
40 ns min Data Hold Time
t
6
0 ns min SYNC High to LDAC Low
t
7
20 ns min LDAC Pulsewidth
t
8
0 ns min LDAC High to SYNC Low
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
SCLK Mark/Space Ratio range is 40/60 to 60/40.
(V
DD
= +10.8 V to +16.5 V, V
SS
= –10.8 V to –16.5 V, GND = O V, R
L
= 2 k⍀, C
L
= 100 pF. All
Specifications T
MIN
to T
MAX
unless otherwise noted.)