Datasheet

SWITCHING CHARACTERISTICS
1, 2
Limit at 25°C Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameters All Grades (B, C Versions) (T, U Versions) Units Conditions/Comments
t
1
0 0 0 ns min Address to WR Setup Time
t
2
0 0 0 ns min Address to WR Hold Time
t
3
70 90 100 ns min Data Valid to WR Setup Time
t
4
10 10 10 ns min Data Valid to WR Hold Time
t
5
95 120 150 ns min Write Pulse Width
NOTES
1
Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, t
R
= t
F
= 5 ns.
2
Timing measurement reference level is
V
INH
+V
INL
2
INTERFACE LOGIC INFORMATION
Address lines A0, A1 and A2 select which DAC accepts data
from the input port. Table I shows the selection table for the
eight DACs with Figure 1 showing the input control logic.
When the
WR signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of
WR. While WR is high, the analog outputs remain
at the value corresponding to the data held in their respective
latches.
Table I. AD7228A Truth Table
AD7228A Control Inputs AD7228A
WR A2 A1 A0 Operation
H X X X No Operation
Device Not Selected
LLLL DAC 1 Transparent
g L L L DAC 1 Latched
LLLH DAC 2 Transparent
L L H L DAC 3 Transparent
L L H H DAC 4 Transparent
L H L L DAC 5 Transparent
L H L H DAC 6 Transparent
L H H L DAC 7 Transparent
L H H H DAC 8 Transparent
H = High State L = Low State X = Don’t Care
+5 V SUPPLY OPERATION
BCTU
Parameter Version Version Version Version Units Conditions/Comments
STATIC PERFORMANCE
Resolution 8888Bits
Relative Accuracy ±2 ±2 ±2 ±2 LSB max
Differential Nonlinearity ±1 ±1 ±1 ±1 LSB max Guaranteed Monotonic
Full-Scale Error ±4 ±2 ±4 ±2 LSB max
Zero Code Error
@ 25°C ±30 ±20 ±30 ±20 mV max
T
MIN
to T
MAX
±40 ±30 ±40 ±30 mV max
REFERENCE INPUT
Reference Input Range 1.2 1.2 1.2 1.2 V min
1.3 1.3 1.3 1.3 V max
Reference Input Resistance 2222kΩ min
Reference Input Capacitance 500 500 500 500 pF max
POWER REQUIREMENTS
Positive Supply Range 4.75/5.25 4.75/5.25 4.75/5.25 4.75/5.25 V min/V max For Specified Performance
Positive Supply Current
@ 25°C 16161616µA max
T
MIN
to T
MAX
20 20 22 22 µA max
Negative Supply Current
@ 25°C 14141414µA max
T
MIN
to T
MAX
18 18 20 20 µA max
NOTES
All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when V
SS
= 0 V.
Specifications subject to change without notice.
(V
DD
= +5 V 6 5%, V
SS
; = 0 to –5 V 6 10%, GND = 0 V, V
REF
= +1.25 V, R
L
= 2 kV, C
L
= 100 pF
unless otherwise noted.) AII specifications T
MIN
to T
MAX
unless otherwise noted.
(See Figures 1, 2; V
DD
= +5 V 6 5% or +10.8 V to +16.5 V; V
SS
= 0 V or –5 V 6 10%)
Figure 1. Input Control Logic
Figure 2. Write Cycle Timing Diagram
AD7228A
REV. A
–3–